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Fix the ALU sensitivity list

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Christoph Urlacher
2023-03-29 14:31:45 +02:00
parent c07c736de9
commit d57673d5a4
1 changed files with 7 additions and 2 deletions
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9
ALU.sv
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@ -15,6 +15,8 @@ module ALU(
output var logic[7:0] result output var logic[7:0] result
); );
// This is a var logic, because I only want a single driver.
// It should be synthesized to a wire, as nothing is stored (hopefully?).
var logic[7:0] lu_result; var logic[7:0] lu_result;
LogicalUnit lu( LogicalUnit lu(
.opcode(opcode), .opcode(opcode),
@ -31,8 +33,11 @@ module ALU(
.result(au_result) .result(au_result)
); );
// If the first most significant opcode bit is 0, it is a logical operation. // Originally, I used the same sensitivity list as with the LogicalUnit/ArithmeticUnit:
always_comb case (opcode) // "always @(opcode or operandA or operandB)"
// This didn't work though, the result didn't update correctly.
// TODO: Figure out why
always @(lu_result or au_result) case (opcode)
3'b000, 3'b000,
3'b001, 3'b001,
3'b010, 3'b010,