christoph/quartus-7-segment-counter
1
Fork 0
Code Activity

Update Quartus project

Browse Source
This commit is contained in:
Christoph Urlacher
2023-03-23 21:44:29 +01:00
parent 91b9363797
commit e0e44eabf2
2 changed files with 14 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
7Seg_Counter_nativelink_simulation.rpt
View File

@ -1,22 +1,23 @@
Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
========= EDA Simulation Settings =====================
Sim Mode : Gate
Sim Mode : RTL
Family : cyclonev
Quartus root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/linux64/
Quartus sim root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/eda/sim_lib
Simulation Tool : modelsim-altera
Simulation Language : verilog
Simulation Mode : GUI
Sim Output File : 7Seg_Counter.vo
Sim SDF file : 7Seg_Counter__verilog.sdo
Sim Output File :
Sim SDF file :
Sim dir : simulation/modelsim
=======================================================
Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File 7Seg_Counter_run_msim_gate_verilog.do already exists - backing up current file as 7Seg_Counter_run_msim_gate_verilog.do.bak
Warning: File 7Seg_Counter_run_msim_rtl_verilog.do already exists - backing up current file as 7Seg_Counter_run_msim_rtl_verilog.do.bak11
Info: Spawning ModelSim-Altera Simulation software
Info: NativeLink simulation flow was successful