From e0e44eabf2df01329b0916b084f75bebbd26a073 Mon Sep 17 00:00:00 2001 From: ChUrl Date: Thu, 23 Mar 2023 21:44:29 +0100 Subject: [PATCH] Update Quartus project --- 7Seg_Counter.qsf | 18 +++++++++--------- 7Seg_Counter_nativelink_simulation.rpt | 9 +++++---- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/7Seg_Counter.qsf b/7Seg_Counter.qsf index 1253dd7..6eaf01f 100644 --- a/7Seg_Counter.qsf +++ b/7Seg_Counter.qsf @@ -56,13 +56,8 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name SYSTEMVERILOG_FILE Counter.sv -set_global_assignment -name SYSTEMVERILOG_FILE BinToBcd.sv -set_global_assignment -name SYSTEMVERILOG_FILE SegmentDisplay.sv -set_global_assignment -name SYSTEMVERILOG_FILE SegDriver.sv set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name SYSTEMVERILOG_FILE Counter_TestBench.sv set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH BinToBcd_TestBench -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_NAME Counter_TestBench -section_id eda_simulation @@ -73,12 +68,9 @@ set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 10000 -set_global_assignment -name SYSTEMVERILOG_FILE BinToBcd_TestBench.sv -set_global_assignment -name EDA_TEST_BENCH_FILE Counter_TestBench.sv -section_id Counter_TestBench set_global_assignment -name EDA_TEST_BENCH_NAME BinToBcd_TestBench -section_id eda_simulation set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id BinToBcd_TestBench set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME BinToBcd_TestBench -section_id BinToBcd_TestBench -set_global_assignment -name EDA_TEST_BENCH_FILE BinToBcd_TestBench.sv -section_id BinToBcd_TestBench set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top @@ -114,5 +106,13 @@ set_location_assignment PIN_AC24 -to segments[3][4] set_location_assignment PIN_AC23 -to segments[3][5] set_location_assignment PIN_AC22 -to segments[3][6] set_location_assignment PIN_AA18 -to segments[1][0] +set_global_assignment -name SYSTEMVERILOG_FILE Counter.sv +set_global_assignment -name SYSTEMVERILOG_FILE BinToBcd.sv +set_global_assignment -name SYSTEMVERILOG_FILE SegmentDisplay.sv +set_global_assignment -name SYSTEMVERILOG_FILE SegDriver.sv +set_global_assignment -name SYSTEMVERILOG_FILE Counter_TestBench.sv +set_global_assignment -name SYSTEMVERILOG_FILE BinToBcd_TestBench.sv set_global_assignment -name CDF_FILE output_files/7Seg_Counter.cdf -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name EDA_TEST_BENCH_FILE Counter_TestBench.sv -section_id Counter_TestBench +set_global_assignment -name EDA_TEST_BENCH_FILE BinToBcd_TestBench.sv -section_id BinToBcd_TestBench \ No newline at end of file diff --git a/7Seg_Counter_nativelink_simulation.rpt b/7Seg_Counter_nativelink_simulation.rpt index b2e68ff..2be2b79 100644 --- a/7Seg_Counter_nativelink_simulation.rpt +++ b/7Seg_Counter_nativelink_simulation.rpt @@ -1,22 +1,23 @@ Info: Start Nativelink Simulation process +Info: NativeLink has detected Verilog design -- Verilog simulation models will be used ========= EDA Simulation Settings ===================== -Sim Mode : Gate +Sim Mode : RTL Family : cyclonev Quartus root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/linux64/ Quartus sim root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/eda/sim_lib Simulation Tool : modelsim-altera Simulation Language : verilog Simulation Mode : GUI -Sim Output File : 7Seg_Counter.vo -Sim SDF file : 7Seg_Counter__verilog.sdo +Sim Output File : +Sim SDF file : Sim dir : simulation/modelsim ======================================================= Info: Starting NativeLink simulation with ModelSim-Altera software Sourced NativeLink script /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/common/tcl/internal/nativelink/modelsim.tcl -Warning: File 7Seg_Counter_run_msim_gate_verilog.do already exists - backing up current file as 7Seg_Counter_run_msim_gate_verilog.do.bak +Warning: File 7Seg_Counter_run_msim_rtl_verilog.do already exists - backing up current file as 7Seg_Counter_run_msim_rtl_verilog.do.bak11 Info: Spawning ModelSim-Altera Simulation software Info: NativeLink simulation flow was successful