Add Quartus project files

2023-03-23 21:30:23 +01:00
parent d5670b0087
commit 91b9363797
6 changed files with 394 additions and 0 deletions
--- a/7Seg_Counter.qsf
+++ b/7Seg_Counter.qsf
@ -0,0 +1,118 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 12:04:29  März 23, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		7Seg_Counter_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CGXFC5C6F27C7
+set_global_assignment -name TOP_LEVEL_ENTITY SegmentDisplay
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:04:29  MäRZ 23, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "10 ns" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name SYSTEMVERILOG_FILE Counter.sv
+set_global_assignment -name SYSTEMVERILOG_FILE BinToBcd.sv
+set_global_assignment -name SYSTEMVERILOG_FILE SegmentDisplay.sv
+set_global_assignment -name SYSTEMVERILOG_FILE SegDriver.sv
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SYSTEMVERILOG_FILE Counter_TestBench.sv
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH BinToBcd_TestBench -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME Counter_TestBench -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Counter_TestBench
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Counter_TestBench -section_id Counter_TestBench
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 10000
+set_global_assignment -name SYSTEMVERILOG_FILE BinToBcd_TestBench.sv
+set_global_assignment -name EDA_TEST_BENCH_FILE Counter_TestBench.sv -section_id Counter_TestBench
+set_global_assignment -name EDA_TEST_BENCH_NAME BinToBcd_TestBench -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id BinToBcd_TestBench
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME BinToBcd_TestBench -section_id BinToBcd_TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE BinToBcd_TestBench.sv -section_id BinToBcd_TestBench
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name BOARD "Cyclone V GX Starter Kit"
+set_location_assignment PIN_Y16 -to clock
+set_location_assignment PIN_Y15 -to reset
+set_location_assignment PIN_AE19 -to decrement
+set_location_assignment PIN_V19 -to segments[0][0]
+set_location_assignment PIN_V18 -to segments[0][1]
+set_location_assignment PIN_V17 -to segments[0][2]
+set_location_assignment PIN_W18 -to segments[0][3]
+set_location_assignment PIN_Y20 -to segments[0][4]
+set_location_assignment PIN_Y19 -to segments[0][5]
+set_location_assignment PIN_Y18 -to segments[0][6]
+set_location_assignment PIN_AD26 -to segments[1][1]
+set_location_assignment PIN_AB19 -to segments[1][2]
+set_location_assignment PIN_AE26 -to segments[1][3]
+set_location_assignment PIN_AE25 -to segments[1][4]
+set_location_assignment PIN_AC19 -to segments[1][5]
+set_location_assignment PIN_AF24 -to segments[1][6]
+set_location_assignment PIN_AD7 -to segments[2][0]
+set_location_assignment PIN_AD6 -to segments[2][1]
+set_location_assignment PIN_U20 -to segments[2][2]
+set_location_assignment PIN_V22 -to segments[2][3]
+set_location_assignment PIN_V20 -to segments[2][4]
+set_location_assignment PIN_W21 -to segments[2][5]
+set_location_assignment PIN_W20 -to segments[2][6]
+set_location_assignment PIN_Y24 -to segments[3][0]
+set_location_assignment PIN_Y23 -to segments[3][1]
+set_location_assignment PIN_AA23 -to segments[3][2]
+set_location_assignment PIN_AA22 -to segments[3][3]
+set_location_assignment PIN_AC24 -to segments[3][4]
+set_location_assignment PIN_AC23 -to segments[3][5]
+set_location_assignment PIN_AC22 -to segments[3][6]
+set_location_assignment PIN_AA18 -to segments[1][0]
+set_global_assignment -name CDF_FILE output_files/7Seg_Counter.cdf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top