From 91b9363797e24a990dbfad815c0c17865df17bb1 Mon Sep 17 00:00:00 2001 From: ChUrl Date: Thu, 23 Mar 2023 21:30:23 +0100 Subject: [PATCH] Add Quartus project files --- 7Seg_Counter.qpf | 31 +++++++ 7Seg_Counter.qsf | 118 +++++++++++++++++++++++++ 7Seg_Counter_nativelink_simulation.rpt | 22 +++++ BinToBcd_TestBench.sv | 58 ++++++++++++ Counter_TestBench.sv | 77 ++++++++++++++++ c5_pin_model_dump.txt | 88 ++++++++++++++++++ 6 files changed, 394 insertions(+) create mode 100644 7Seg_Counter.qpf create mode 100644 7Seg_Counter.qsf create mode 100644 7Seg_Counter_nativelink_simulation.rpt create mode 100644 BinToBcd_TestBench.sv create mode 100644 Counter_TestBench.sv create mode 100644 c5_pin_model_dump.txt diff --git a/7Seg_Counter.qpf b/7Seg_Counter.qpf new file mode 100644 index 0000000..fd4db8f --- /dev/null +++ b/7Seg_Counter.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 12:04:29 März 23, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "12:04:29 März 23, 2023" + +# Revisions + +PROJECT_REVISION = "7Seg_Counter" diff --git a/7Seg_Counter.qsf b/7Seg_Counter.qsf new file mode 100644 index 0000000..1253dd7 --- /dev/null +++ b/7Seg_Counter.qsf @@ -0,0 +1,118 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 12:04:29 März 23, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# 7Seg_Counter_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY SegmentDisplay +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:04:29 MäRZ 23, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "10 ns" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name SYSTEMVERILOG_FILE Counter.sv +set_global_assignment -name SYSTEMVERILOG_FILE BinToBcd.sv +set_global_assignment -name SYSTEMVERILOG_FILE SegmentDisplay.sv +set_global_assignment -name SYSTEMVERILOG_FILE SegDriver.sv +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name SYSTEMVERILOG_FILE Counter_TestBench.sv +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH BinToBcd_TestBench -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME Counter_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Counter_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Counter_TestBench -section_id Counter_TestBench +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 10000 +set_global_assignment -name SYSTEMVERILOG_FILE BinToBcd_TestBench.sv +set_global_assignment -name EDA_TEST_BENCH_FILE Counter_TestBench.sv -section_id Counter_TestBench +set_global_assignment -name EDA_TEST_BENCH_NAME BinToBcd_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id BinToBcd_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME BinToBcd_TestBench -section_id BinToBcd_TestBench +set_global_assignment -name EDA_TEST_BENCH_FILE BinToBcd_TestBench.sv -section_id BinToBcd_TestBench +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name BOARD "Cyclone V GX Starter Kit" +set_location_assignment PIN_Y16 -to clock +set_location_assignment PIN_Y15 -to reset +set_location_assignment PIN_AE19 -to decrement +set_location_assignment PIN_V19 -to segments[0][0] +set_location_assignment PIN_V18 -to segments[0][1] +set_location_assignment PIN_V17 -to segments[0][2] +set_location_assignment PIN_W18 -to segments[0][3] +set_location_assignment PIN_Y20 -to segments[0][4] +set_location_assignment PIN_Y19 -to segments[0][5] +set_location_assignment PIN_Y18 -to segments[0][6] +set_location_assignment PIN_AD26 -to segments[1][1] +set_location_assignment PIN_AB19 -to segments[1][2] +set_location_assignment PIN_AE26 -to segments[1][3] +set_location_assignment PIN_AE25 -to segments[1][4] +set_location_assignment PIN_AC19 -to segments[1][5] +set_location_assignment PIN_AF24 -to segments[1][6] +set_location_assignment PIN_AD7 -to segments[2][0] +set_location_assignment PIN_AD6 -to segments[2][1] +set_location_assignment PIN_U20 -to segments[2][2] +set_location_assignment PIN_V22 -to segments[2][3] +set_location_assignment PIN_V20 -to segments[2][4] +set_location_assignment PIN_W21 -to segments[2][5] +set_location_assignment PIN_W20 -to segments[2][6] +set_location_assignment PIN_Y24 -to segments[3][0] +set_location_assignment PIN_Y23 -to segments[3][1] +set_location_assignment PIN_AA23 -to segments[3][2] +set_location_assignment PIN_AA22 -to segments[3][3] +set_location_assignment PIN_AC24 -to segments[3][4] +set_location_assignment PIN_AC23 -to segments[3][5] +set_location_assignment PIN_AC22 -to segments[3][6] +set_location_assignment PIN_AA18 -to segments[1][0] +set_global_assignment -name CDF_FILE output_files/7Seg_Counter.cdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/7Seg_Counter_nativelink_simulation.rpt b/7Seg_Counter_nativelink_simulation.rpt new file mode 100644 index 0000000..b2e68ff --- /dev/null +++ b/7Seg_Counter_nativelink_simulation.rpt @@ -0,0 +1,22 @@ +Info: Start Nativelink Simulation process + +========= EDA Simulation Settings ===================== + +Sim Mode : Gate +Family : cyclonev +Quartus root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/linux64/ +Quartus sim root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/eda/sim_lib +Simulation Tool : modelsim-altera +Simulation Language : verilog +Simulation Mode : GUI +Sim Output File : 7Seg_Counter.vo +Sim SDF file : 7Seg_Counter__verilog.sdo +Sim dir : simulation/modelsim + +======================================================= + +Info: Starting NativeLink simulation with ModelSim-Altera software +Sourced NativeLink script /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/common/tcl/internal/nativelink/modelsim.tcl +Warning: File 7Seg_Counter_run_msim_gate_verilog.do already exists - backing up current file as 7Seg_Counter_run_msim_gate_verilog.do.bak +Info: Spawning ModelSim-Altera Simulation software +Info: NativeLink simulation flow was successful diff --git a/BinToBcd_TestBench.sv b/BinToBcd_TestBench.sv new file mode 100644 index 0000000..2ba17bf --- /dev/null +++ b/BinToBcd_TestBench.sv @@ -0,0 +1,58 @@ +`default_nettype none + +module BinToBcd_TestBench; + + var logic clock, reset, decrement; + tri[13:0] binout; + + Counter cnt( + .clock(clock), + .reset(reset), + .decrement(decrement), + .binout(binout) + ); + + tri[3:0] value[3:0]; + + BinToBcd bcd( + .binin(binout), + .bcdout(value) + ); + +// synthesis translate_off + integer ii; + initial begin + $timeformat(-9, 2, " ns", 20); + + $display("%0t Reset", $time); + decrement = 0; + #20 reset = 1; + #20 reset = 0; + assert (value[0] == 0); + assert (value[1] == 0); + assert (value[2] == 0); + assert (value[3] == 0); + + $display("%0t Bin[1] = 0 0 0 1", $time); + #20 clock = 1; + #20 clock = 0; + assert (value[0] == 1); + assert (value[1] == 0); + assert (value[2] == 0); + assert (value[3] == 0); + + $display("%0t Bin[1024] = 1 0 2 4", $time); + for (ii = 0; ii < 1023; ii = ii + 1) begin + #20 clock = 1; + #20 clock = 0; + end + assert (value[0] == 4); + assert (value[1] == 2); + assert (value[2] == 0); + assert (value[3] == 1); + + $display("Success!"); + end + +// synthesis translate_on +endmodule \ No newline at end of file diff --git a/Counter_TestBench.sv b/Counter_TestBench.sv new file mode 100644 index 0000000..31d91ab --- /dev/null +++ b/Counter_TestBench.sv @@ -0,0 +1,77 @@ +`default_nettype none + +module Counter_TestBench; + + var logic clock, reset, decrement; + tri[13:0] value; + + Counter cnt( + .clock(clock), + .reset(reset), + .decrement(decrement), + .binout(value) + ); + +// synthesis translate_off + integer ii; + initial begin + $timeformat(-9, 2, " ns", 20); + + $display("%0t Initial Reset", $time); + #20 reset = 1; + #20 reset = 0; + assert (value == 0); + + $display("%0t Increment 1024x", $time); + decrement = 0; + for (ii = 0; ii < 1024; ii = ii + 1) begin + #20 clock = 1; + #20 clock = 0; + assert (value == ii + 1); + end + + $display("%0t Decrement 1024x", $time); + decrement = 1; + for (ii = 1024; ii > 0; ii = ii - 1) begin + #20 clock = 1; + #20 clock = 0; + assert (value == ii - 1); + end + + $display("%0t Increment 1024x", $time); + decrement = 0; + for (ii = 0; ii < 1024; ii = ii + 1) begin + #20 clock = 1; + #20 clock = 0; + assert (value == ii + 1); + end + + $display("%0t Reset", $time); + #20 reset = 1; + #20 reset = 0; + assert (value == 0); + + $display("%0t Increment 9999x", $time); + decrement = 0; + for (ii = 0; ii < 9999; ii = ii + 1) begin + #20 clock = 1; + #20 clock = 0; + assert (value == ii + 1); + end + + $display("%0t Overflow", $time); + #20 clock = 1; + #20 clock = 0; + assert (value == 0); + + $display("%0t Underflow", $time); + decrement = 1; + #20 clock = 1; + #20 clock = 0; + assert (value == 9999); + + $display("Success!"); + end + +// synthesis translate_on +endmodule \ No newline at end of file diff --git a/c5_pin_model_dump.txt b/c5_pin_model_dump.txt new file mode 100644 index 0000000..3a3970c --- /dev/null +++ b/c5_pin_model_dump.txt @@ -0,0 +1,88 @@ +io_4iomodule_c5_index: 61gpio_index: 2 +io_4iomodule_c5_index: 62gpio_index: 348 +io_4iomodule_c5_index: 40gpio_index: 6 +io_4iomodule_c5_index: 59gpio_index: 344 +io_4iomodule_c5_index: 31gpio_index: 10 +io_4iomodule_c5_index: 35gpio_index: 340 +io_4iomodule_c5_index: 42gpio_index: 14 +io_4iomodule_c5_index: 19gpio_index: 336 +io_4iomodule_c5_index: 29gpio_index: 19 +io_4iomodule_c5_index: 9gpio_index: 332 +io_4iomodule_c5_index: 34gpio_index: 22 +io_4iomodule_c5_index: 25gpio_index: 328 +io_4iomodule_c5_index: 17gpio_index: 27 +io_4iomodule_c5_index: 44gpio_index: 324 +io_4iomodule_c5_index: 57gpio_index: 30 +io_4iomodule_c5_index: 13gpio_index: 320 +io_4iomodule_c5_index: 5gpio_index: 35 +io_4iomodule_c5_index: 39gpio_index: 316 +io_4iomodule_c5_index: 14gpio_index: 38 +io_4iomodule_c5_index: 27gpio_index: 312 +io_4iomodule_c5_index: 21gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 308 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 26gpio_index: 304 +io_4iomodule_c5_index: 1gpio_index: 51 +io_4iomodule_c5_index: 38gpio_index: 300 +io_4iomodule_c5_index: 50gpio_index: 54 +io_4iomodule_c5_index: 36gpio_index: 296 +io_4iomodule_c5_index: 11gpio_index: 59 +io_4iomodule_c5_index: 2gpio_index: 292 +io_4iomodule_c5_index: 4gpio_index: 62 +io_4iomodule_c5_index: 6gpio_index: 288 +io_4iomodule_c5_index: 48gpio_index: 67 +io_4iomodule_c5_index: 24gpio_index: 284 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 12gpio_index: 280 +io_4iomodule_c5_index: 49gpio_index: 75 +io_4iomodule_c5_index: 63gpio_index: 276 +io_4iomodule_c5_index: 41gpio_index: 78 +io_4iomodule_c5_index: 37gpio_index: 272 +io_4iomodule_c5_index: 3gpio_index: 83 +io_4iomodule_c5_index: 33gpio_index: 268 +io_4iomodule_c5_index: 22gpio_index: 86 +io_4iomodule_c5_index: 54gpio_index: 264 +io_4iomodule_c5_index: 56gpio_index: 91 +io_4iomodule_c5_index: 32gpio_index: 260 +io_4iomodule_c5_index: 53gpio_index: 94 +io_4iomodule_c5_index: 52gpio_index: 256 +io_4iomodule_c5_index: 28gpio_index: 99 +io_4iomodule_c5_index: 45gpio_index: 252 +io_4iomodule_c5_index: 10gpio_index: 102 +io_4iomodule_c5_index: 43gpio_index: 248 +io_4iomodule_c5_index: 15gpio_index: 107 +io_4iomodule_c5_index: 7gpio_index: 244 +io_4iomodule_c5_index: 55gpio_index: 110 +io_4iomodule_c5_index: 60gpio_index: 240 +io_4iomodule_c5_index: 18gpio_index: 115 +io_4iomodule_c5_index: 58gpio_index: 236 +io_4iomodule_c5_index: 46gpio_index: 118 +io_4iomodule_c5_index: 30gpio_index: 232 +io_4iomodule_c5_index: 16gpio_index: 123 +io_4iomodule_c5_index: 47gpio_index: 228 +io_4iomodule_c5_index: 51gpio_index: 126 +io_4iomodule_c5_index: 23gpio_index: 224 +io_4iomodule_h_c5_index: 0gpio_index: 129 +io_4iomodule_h_c5_index: 18gpio_index: 133 +io_4iomodule_h_c5_index: 15gpio_index: 137 +io_4iomodule_h_c5_index: 16gpio_index: 141 +io_4iomodule_h_c5_index: 20gpio_index: 144 +io_4iomodule_h_c5_index: 23gpio_index: 148 +io_4iomodule_h_c5_index: 12gpio_index: 152 +io_4iomodule_h_c5_index: 9gpio_index: 156 +io_4iomodule_h_c5_index: 1gpio_index: 160 +io_4iomodule_h_c5_index: 5gpio_index: 164 +io_4iomodule_h_c5_index: 21gpio_index: 168 +io_4iomodule_h_c5_index: 6gpio_index: 172 +io_4iomodule_h_c5_index: 17gpio_index: 176 +io_4iomodule_h_c5_index: 2gpio_index: 180 +io_4iomodule_h_c5_index: 4gpio_index: 184 +io_4iomodule_h_c5_index: 3gpio_index: 188 +io_4iomodule_h_c5_index: 14gpio_index: 192 +io_4iomodule_h_c5_index: 7gpio_index: 196 +io_4iomodule_h_c5_index: 19gpio_index: 200 +io_4iomodule_h_c5_index: 11gpio_index: 204 +io_4iomodule_h_c5_index: 8gpio_index: 208 +io_4iomodule_h_c5_index: 13gpio_index: 212 +io_4iomodule_h_c5_index: 22gpio_index: 216 +io_4iomodule_h_c5_index: 10gpio_index: 220