51 lines
2.3 KiB
Markdown
51 lines
2.3 KiB
Markdown
# README
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This repository contains multiple small CPUs, simulated in Logisim.
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**I abandoned this in favor of [this](https://gitlab.com/ChUrl/quartus-8-bit-cpu).**
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## Models
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### cpu8_v1
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Extremely simple 8-bit CPU with 6 arithmetic (ADD, SUB) and logical (AND, OR, NAND, NOR) operations, conditional jumps are also supported.
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The CPU has 6 Registers:
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- 1x Constant loading
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- 2x ALU operand
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- 1x ALU result
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- 2x General purpose
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The program is read from a readonly memory (ROM).
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#### Instruction Reference:
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The Instruction/Data share 8-bit, the instruction mode is specified by bits 6 and 7, so there is a total of 4 modes:
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| Bit | Value | Description |
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|-----|--------|-----------------------|
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| 6:7 | 00 | Constant loading mode |
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| 0:5 | xxxxxx | Number value |
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| Bit | Value | Description |
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|-----|----------------------------------------|----------------------------------------|
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| 6:7 | 01 | ALU mode |
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| 3:5 | 000 | Reserved |
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| 0:2 | 000<br>001<br>010<br>011<br>100<br>101 | And<br>Or<br>Nand<br>Nor<br>Add<br>Sub |
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| Bit | Value | Description |
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|-----|-------|---------------------------|
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| 6:7 | 10 | Copy mode |
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| 3:5 | xxx | Source register or input |
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| 0:2 | xxx | Target register or output |
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| Bit | Value | Description |
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|-----|------------------------------------------------------|-----------------------------------------------------------------|
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| 6:7 | 11 | Jump mode |
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| 3:5 | 000 | Reserved |
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| 0:2 | 000<br>001<br>010<br>011<br>100<br>101<br>110<br>111 | Never<br>== 0<br>< 0<br><= 0<br>Always<br>!= 0<br>> 0<br>>= 0 |
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## Programming
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In [this repository](https://gitlab.com/ChUrl/logisim-assembler) I implemented a simple assembler, to make programming the CPUs easier.
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The assembler versions (branches) match with the CPU names.
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