164 lines
7.0 KiB
TeX
164 lines
7.0 KiB
TeX
\makeglossaries{}
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% Acronyms
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\newacronym{acpi}{ACPI}{advanced configuration and power interface}
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\newacronym{aml}{AML}{acpi machine language}
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\newacronym{ap}{AP}{\gls{application processor}}
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\newacronym{apr}{APR}{arbitration priority register}
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\newacronym{apic}{APIC}{advanced programmable interrupt controller}
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\newacronym{bios}{BIOS}{basic input/output system}
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\newacronym{bsp}{BSP}{\gls{bootstrap processor}}
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\newacronym{cpuid}{CPUID}{cpu identification}
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\newacronym{eoi}{EOI}{end of interrupt}
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\newacronym{esr}{ESR}{error status register}
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\newacronym{gdt}{GDT}{global descriptor table}
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\newacronym{gdtr}{GDTR}{global descriptor table register}
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\newacronym{gsi}{GSI}{\gls{global system interrupt}}
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\newacronym{ich}{ICH}{intel input/output controller hub}
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\newacronym{icr}{ICR}{\gls{interrupt command register}}
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\newacronym{idt}{IDT}{interrupt descriptor table}
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\newacronym{idtr}{IDTR}{interrupt descriptor table register}
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\newacronym{imcr}{IMCR}{\gls{interrupt mode control register}}
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\newacronym{imr}{IMR}{interrupt mask register}
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\newacronym{inti}{INTI}{interrupt input}
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\newacronym{ipi}{IPI}{inter-processor interrupt}
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\newacronym{irq}{IRQ}{interrupt request}
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\newacronym{irr}{IRR}{\gls{interrupt request register}}
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\newacronym{isa}{ISA}{industry standard architecture}
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\newacronym{isr}{ISR}{\gls{in-service register}}
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\newacronym{lvt}{LVT}{\gls{local vector table}}
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\newacronym{madt}{MADT}{multiple apic descriptor table}
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\newacronym{mmio}{MMIO}{memory mapped input/output}
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\newacronym{msr}{MSR}{model specific register}
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\newacronym{msi}{MSI}{\gls{message-signaled interrupt}}
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\newacronym{nmi}{NMI}{non-maskable interrupt}
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\newacronym{pci}{PCI}{peripheral component interconnect}
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\newacronym{pic}{PIC}{programmable interrupt controller}
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\newacronym{pit}{PIT}{programmable interval timer}
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\newacronym{redtbl}{REDTBL}{redirection table}
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\newacronym{sipi}{SIPI}{startup inter-processor interrupt}
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\newacronym{smi}{SMI}{system management interrupt}
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\newacronym{smp}{SMP}{symmetric multiprocessing}
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\newacronym{svr}{SVR}{\gls{spurious interrupt vector register}}
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\newacronym{tmr}{TMR}{trigger-mode register}
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\newacronym{tpr}{TPR}{\gls{task-priority register}}
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\newacronym{tss}{TSS}{task state segment}
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\newacronym{uefi}{UEFI}{unified extensible firmware interface}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% Glossary Entries
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% \newglossaryentry{}{
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% name={},
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% description={}
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% }
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\newglossaryentry{apic timer}{%
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name={APIC timer},
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description={a hardware timer that can trigger periodic interrupts by using a counter, integrated into the local APIC}
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}
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\newglossaryentry{application processor}{%
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name={application processor},
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description={a processor inside an SMP system, e.g.\ a CPU core}
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}
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\newglossaryentry{bootstrap processor}{%
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name={bootstrap processor},
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description={the application processor used to boot an SMP system}
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}
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\newglossaryentry{discrete apic}{%
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name={discrete APIC},
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description={the predecessor of the xApic architecture where the local APIC was not integrated into the CPU core, register access is handled through MMIO}
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}
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\newglossaryentry{global system interrupt}{%
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name={global system interrupt},
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description={an abstraction used by ACPI to decouple interrupts from hardware interrupt lines}
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}
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\newglossaryentry{io apic}{%
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name={I/O APIC},
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description={a part of the APIC architecture inside the chipset, responsible for receiving external interrupts}
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}
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\newglossaryentry{init ipi}{%
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name={INIT IPI},
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description={an interprocessor interrupt sent from the BSP to the APs, to begin the AP initialization process}
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}
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\newglossaryentry{inter-processor interrupt}{%
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name={inter-processor interrupt},
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description={an interrupt sent between CPU cores}
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}
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\newglossaryentry{interrupt command register}{%
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name={interrupt command register},
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description={a register of the local APIC used to issue interprocessor interrupts}
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}
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\newglossaryentry{interrupt mode control register}{%
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name={interrupt mode control register},
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description={a register present in some systems to choose the physically connected interrupt controller}
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}
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\newglossaryentry{interrupt request register}{%
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name={interrupt request register},
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description={a register, part of the PIC and local APIC, which keeps track of received interrupts}
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}
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\newglossaryentry{in-service register}{%
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name={in-service register},
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description={a register, part of the PIC and local APIC, which keeps track of interrupts that are being serviced}
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}
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\newglossaryentry{irq override}{%
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name={interrupt override},
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description={information from ACPI, that describes how interrupt lines correspond to global system interrupts}
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}
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\newglossaryentry{local apic}{%
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name={local APIC},
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description={a part of the APIC architecture inside a CPU core, responsible for receiving local interrupts and communication with the I/O APIC}
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}
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\newglossaryentry{local interrupt}{%
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name={local interrupt},
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description={an CPU internal interrupt handled by the local APIC, like the APIC timer interrupt}
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}
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\newglossaryentry{local vector table}{%
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name={local vector table},
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description={a set of registers, part of the local APIC, that configure how local interrupts are handled}
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}
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\newglossaryentry{message-signaled interrupt}{%
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name={message-signaled interrupt},
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description={an interrupt sent in-band over a PCI-bus}
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}
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\newglossaryentry{pic mode}{%
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name={PIC mode},
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description={only use the PIC for interrupt handling, like the PC/AT}
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}
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\newglossaryentry{redirection table}{%
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name={redirection table},
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description={a set of registers, part of the I/O APIC, that configure how external interrupts are handled}
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}
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\newglossaryentry{spurious interrupt vector register}{%
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name={spurious interrupt vector register},
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description={a register of the local APIC which contains the APIC software enable flag and the spurious interrupt vector}
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}
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\newglossaryentry{startup ipi}{%
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name={STARTUP IPI},
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description={an interprocessor interrupt sent from the BSP to the APs, to load the AP startup routine and finish AP initialization}
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}
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\newglossaryentry{symmetric io mode}{%
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name={symmetric I/O mode},
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description={use the I/O APIC in combination with the local APIC for interrupt handling in multiprocessor systems}
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}
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\newglossaryentry{task-priority register}{%
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name={task-priority register},
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description={a register of the local APIC which determines interrupt handling order and priority theshold}
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}
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\newglossaryentry{virtual wire mode}{%
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name={virtual wire mode},
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description={use the local APIC in combination with the PIC as external interrupt controller}
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}
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\newglossaryentry{xapic}{%
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name={xApic},
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description={a revision of the APIC architecture, register access is handled through MMIO}
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}
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\newglossaryentry{x2apic}{%
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name={x2Apic},
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description={a revision of the APIC architecture, register access is handled through MSRs}
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}
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