\makeglossaries{}

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% Acronyms
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\newacronym{acpi}{ACPI}{advanced configuration and power interface}
\newacronym{aml}{AML}{acpi machine language}
\newacronym{ap}{AP}{\gls{application processor}}
\newacronym{apr}{APR}{arbitration priority register}
\newacronym{apic}{APIC}{advanced programmable interrupt controller}
\newacronym{bios}{BIOS}{basic input/output system}
\newacronym{bsp}{BSP}{\gls{bootstrap processor}}
\newacronym{cpuid}{CPUID}{cpu identification}
\newacronym{eoi}{EOI}{end of interrupt}
\newacronym{esr}{ESR}{error status register}
\newacronym{gdt}{GDT}{global descriptor table}
\newacronym{gdtr}{GDTR}{global descriptor table register}
\newacronym{gsi}{GSI}{\gls{global system interrupt}}
\newacronym{ich}{ICH}{intel input/output controller hub}
\newacronym{icr}{ICR}{\gls{interrupt command register}}
\newacronym{idt}{IDT}{interrupt descriptor table}
\newacronym{idtr}{IDTR}{interrupt descriptor table register}
\newacronym{imcr}{IMCR}{\gls{interrupt mode control register}}
\newacronym{imr}{IMR}{interrupt mask register}
\newacronym{inti}{INTI}{interrupt input}
\newacronym{ipi}{IPI}{inter-processor interrupt}
\newacronym{irq}{IRQ}{interrupt request}
\newacronym{irr}{IRR}{\gls{interrupt request register}}
\newacronym{isa}{ISA}{industry standard architecture}
\newacronym{isr}{ISR}{\gls{in-service register}}
\newacronym{lvt}{LVT}{\gls{local vector table}}
\newacronym{madt}{MADT}{multiple apic descriptor table}
\newacronym{mmio}{MMIO}{memory mapped input/output}
\newacronym{msr}{MSR}{model specific register}
\newacronym{msi}{MSI}{\gls{message-signaled interrupt}}
\newacronym{nmi}{NMI}{non-maskable interrupt}
\newacronym{pci}{PCI}{peripheral component interconnect}
\newacronym{pic}{PIC}{programmable interrupt controller}
\newacronym{pit}{PIT}{programmable interval timer}
\newacronym{redtbl}{REDTBL}{redirection table}
\newacronym{sipi}{SIPI}{startup inter-processor interrupt}
\newacronym{smi}{SMI}{system management interrupt}
\newacronym{smp}{SMP}{symmetric multiprocessing}
\newacronym{svr}{SVR}{\gls{spurious interrupt vector register}}
\newacronym{tmr}{TMR}{trigger-mode register}
\newacronym{tpr}{TPR}{\gls{task-priority register}}
\newacronym{tss}{TSS}{task state segment}
\newacronym{uefi}{UEFI}{unified extensible firmware interface}

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% Glossary Entries
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% \newglossaryentry{}{
%   name={},
%   description={}
% }

\newglossaryentry{apic timer}{%
  name={APIC timer},
  description={a hardware timer that can trigger periodic interrupts by using a counter, integrated into the local APIC}
}
\newglossaryentry{application processor}{%
  name={application processor},
  description={a processor inside an SMP system, e.g.\ a CPU core}
}
\newglossaryentry{bootstrap processor}{%
  name={bootstrap processor},
  description={the application processor used to boot an SMP system}
}
\newglossaryentry{discrete apic}{%
  name={discrete APIC},
  description={the predecessor of the xApic architecture where the local APIC was not integrated into the CPU core, register access is handled through MMIO}
}
\newglossaryentry{global system interrupt}{%
  name={global system interrupt},
  description={an abstraction used by ACPI to decouple interrupts from hardware interrupt lines}
}
\newglossaryentry{io apic}{%
  name={I/O APIC},
  description={a part of the APIC architecture inside the chipset, responsible for receiving external interrupts}
}
\newglossaryentry{init ipi}{%
  name={INIT IPI},
  description={an interprocessor interrupt sent from the BSP to the APs, to begin the AP initialization process}
}
\newglossaryentry{inter-processor interrupt}{%
  name={inter-processor interrupt},
  description={an interrupt sent between CPU cores}
}
\newglossaryentry{interrupt command register}{%
  name={interrupt command register},
  description={a register of the local APIC used to issue interprocessor interrupts}
}
\newglossaryentry{interrupt mode control register}{%
  name={interrupt mode control register},
  description={a register present in some systems to choose the physically connected interrupt controller}
}
\newglossaryentry{interrupt request register}{%
  name={interrupt request register},
  description={a register, part of the PIC and local APIC, which keeps track of received interrupts}
}
\newglossaryentry{in-service register}{%
  name={in-service register},
  description={a register, part of the PIC and local APIC, which keeps track of interrupts that are being serviced}
}
\newglossaryentry{irq override}{%
  name={interrupt override},
  description={information from ACPI, that describes how interrupt lines correspond to global system interrupts}
}
\newglossaryentry{local apic}{%
  name={local APIC},
  description={a part of the APIC architecture inside a CPU core, responsible for receiving local interrupts and communication with the I/O APIC}
}
\newglossaryentry{local interrupt}{%
  name={local interrupt},
  description={an CPU internal interrupt handled by the local APIC, like the APIC timer interrupt}
}
\newglossaryentry{local vector table}{%
  name={local vector table},
  description={a set of registers, part of the local APIC, that configure how local interrupts are handled}
}
\newglossaryentry{message-signaled interrupt}{%
  name={message-signaled interrupt},
  description={an interrupt sent in-band over a PCI-bus}
}
\newglossaryentry{pic mode}{%
  name={PIC mode},
  description={only use the PIC for interrupt handling, like the PC/AT}
}
\newglossaryentry{redirection table}{%
  name={redirection table},
  description={a set of registers, part of the I/O APIC, that configure how external interrupts are handled}
}
\newglossaryentry{spurious interrupt vector register}{%
  name={spurious interrupt vector register},
  description={a register of the local APIC which contains the APIC software enable flag and the spurious interrupt vector}
}
\newglossaryentry{startup ipi}{%
  name={STARTUP IPI},
  description={an interprocessor interrupt sent from the BSP to the APs, to load the AP startup routine and finish AP initialization}
}
\newglossaryentry{symmetric io mode}{%
  name={symmetric I/O mode},
  description={use the I/O APIC in combination with the local APIC for interrupt handling in multiprocessor systems}
}
\newglossaryentry{task-priority register}{%
  name={task-priority register},
  description={a register of the local APIC which determines interrupt handling order and priority theshold}
}
\newglossaryentry{virtual wire mode}{%
  name={virtual wire mode},
  description={use the local APIC in combination with the PIC as external interrupt controller}
}
\newglossaryentry{xapic}{%
  name={xApic},
  description={a revision of the APIC architecture, register access is handled through MMIO}
}
\newglossaryentry{x2apic}{%
  name={x2Apic},
  description={a revision of the APIC architecture, register access is handled through MSRs}
}
