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Sync with BSuSP

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2023-03-02 22:10:11 +01:00
parent daf0161df5
commit 9a62332d70
4 changed files with 8 additions and 34 deletions

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@ -1,7 +1,7 @@
<div align="center">
<img src="https://coconucos.cs.hhu.de/lehre/bigdata/resources/img/hhu-logo.svg" width=300>
[![Download](https://img.shields.io/static/v1?label=&message=pdf&color=EE3F24&style=for-the-badge&logo=adobe-acrobat-reader&logoColor=FFFFFF)](/../-/jobs/artifacts/main/file/thesis.pdf?job=latex)
[![Download](https://img.shields.io/static/v1?label=&message=pdf&color=EE3F24&style=for-the-badge&logo=adobe-acrobat-reader&logoColor=FFFFFF)](/../-/jobs/artifacts/master/file/document/thesis.pdf?job=latex)
</div>
# :notebook: &nbsp; Aufgabenbeschreibung
@ -76,8 +76,7 @@ $ ./run.sh --bios true --file hhuOS.iso
- `src/device/interrupt/apic/*`
- `src/device/time/ApicTimer.*`
- `src/device/cpu/Smp.*`
- `src/device/cpu/smp.asm`
- `src/device/cpu/smp_*`
# Commit history

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@ -1,7 +1,9 @@
\chapter{Figures}
\label{ch:figures}
\begin{figure}[h]
\clearpage
\begin{figure}[H]
\centering
\begin{subfigure}[b]{0.85\textwidth}
\includesvg[width=1.0\linewidth]{diagrams/apic_enable_seq.svg}
@ -10,7 +12,7 @@
\label{fig:apicenable}
\end{figure}
\begin{figure}[h]
\begin{figure}[H]
\centering
\begin{subfigure}[b]{0.85\textwidth}
\includesvg[width=1.0\linewidth]{diagrams/apic_smp_enable_seq.svg}

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@ -38,7 +38,7 @@ Specifically, QEMU provides the current register state of all local and I/O APIC
\end{itemize}
Although hhuOS is developed mainly for learning purposes, every OS' core task remains to be the management of computer hardware.
For this reason, this implementation was additionally tested on a \textquote{ThinkPad T60s} with an Intel \textquote{Core 2 Duo} processor.
For this reason, this implementation was additionally tested on a \textquote{ThinkPad X60s} with an Intel \textquote{Core 2 Duo} processor.
By providing internal status data through the virtual file system, implemented features (including booting additional APs) were verified on this very specific set of hardware.
More specifically, information about detected and enabled local APICs and the I/O APIC, register values from the BSP's LVT and the REDTBL, the contents of the PIC's \textbf{\gls{imr}}, and the number of occurred interrupts by core (similar to \code{/proc/interrupts} in Linux~\autocite{linux}) are exposed on the path \code{/device/apic/}.
@ -54,7 +54,7 @@ This way, the following things could be verified on real hardware:
Interestingly, this was easier to verify on real hardware than in QEMU, because QEMU usually instantly crashes when interrupts are enabled on an AP beside the BSP\@.
Also, redirecting the keyboard interrupt in QEMU significantly changes the behavior of any key press and renders the keyboard unusable.
This is expected, as hhuOS' paging is not designed for multiple processors.
On the ThinkPad T60s though, it was possible (surprisingly) to use the redirected keyboard interrupt to \code{cat} the \code{/device/apic/irqs} file to observe the interrupt statistics, which showed the keyboard interrupts indeed arriving at a different core than the BSP\@.
On the ThinkPad X60s though, it was possible (surprisingly) to use the redirected keyboard interrupt to \code{cat} the \code{/device/apic/irqs} file to observe the interrupt statistics, which showed the keyboard interrupts indeed arriving at a different core than the BSP\@.
After a certain time, the system crashes on the ThinkPad as well.}.
\end{itemize}

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@ -6,9 +6,6 @@
urldate = {2023-02-08},
year = {1978},
note = {Rev 3},
comment = {Datasheet for Intel's Programmable Interrupt Controller},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 8259A Datasheet.pdf:PDF},
keywords = {PIC},
}
@Manual{ia32,
@ -18,9 +15,6 @@
url = {https://cdrdv2.intel.com/v1/dl/getContent/671200},
urldate = {2023-02-08},
year = {2022},
abstract = {The general manual for Intel's 32 bit and 64 bit architectures},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 64 and IA-32 Manual.pdf:PDF},
keywords = {x86, Intel 64, Intel IA-32},
}
@Manual{ioapic,
@ -30,9 +24,6 @@
url = {https://pdos.csail.mit.edu/6.828/2017/readings/ia32/ioapic.pdf},
urldate = {2023-02-08},
year = {1996},
comment = {Datasheet of Intel's external I/O APIC},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 82093AA Datasheet.pdf:PDF},
keywords = {I/O APIC},
}
@Manual{acpi1,
@ -43,7 +34,6 @@
urldate = {2023-02-08},
year = {1999},
note = {Rev 1.0b},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/ACPI 1 Specification.pdf:PDF},
}
@Manual{acpi2,
@ -54,7 +44,6 @@
urldate = {2023-02-08},
year = {2003},
note = {Rev 2.0c},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/ACPI 2 Specification.pdf:PDF},
}
@Manual{acpi65,
@ -65,8 +54,6 @@
urldate = {2023-02-08},
year = {2022},
note = {Rev 6.5},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/ACPI 6_5 Specification.pdf:PDF},
keywords = {ACPI Specification, UEFI},
}
@Manual{cpp20draft,
@ -77,8 +64,6 @@
urldate = {2023-02-08},
year = {2020},
note = {N4860},
abstract = {C++ Draft International Standard},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/C++20 Standard Draft.pdf:PDF},
}
@Manual{c99draft,
@ -89,8 +74,6 @@
urldate = {2023-02-08},
year = {1999},
note = {N1256},
abstract = {Programming languages - C},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/C99 Standard Draft.pdf:PDF},
}
@Manual{ich2,
@ -100,7 +83,6 @@
url = {https://www.intel.com/content/dam/doc/datasheet/82801ba-i-o-controller-hub-2-82801bam-i-o-controller-hub-2-mobile-datasheet.pdf},
urldate = {2023-02-08},
year = {2000},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel ICH2 Datasheet.pdf:PDF},
}
@Manual{ich5,
@ -111,7 +93,6 @@
urldate = {2023-02-08},
year = {2003},
note = {Rev 001},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel ICH5 Datasheet.pdf:PDF},
}
@Manual{mpspec,
@ -122,7 +103,6 @@
urldate = {2023-02-08},
year = {1997},
note = {Rev 1.4},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel MultiProcessor Specification.pdf:PDF},
}
@TechReport{msilatency,
@ -132,7 +112,6 @@
year = {2009},
month = jan,
type = {techreport},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel Reducing Interrupt Latency through the Use of MSIs Whitepaper.pdf:PDF},
url = {https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf},
}
@ -143,7 +122,6 @@
url = {https://www.scss.tcd.ie/~jones/CS4021/processor-identification-cpuid-instruction-note.pdf},
urldate = {2023-02-08},
year = {2012},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel CPUID Application Note.pdf:PDF},
}
@Misc{hhuos,
@ -163,7 +141,6 @@
urldate = {2023-02-08},
year = {1998},
note = {Rev 2.2},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/PCI 2_2 Specification.pdf:PDF},
}
@Manual{pcat,
@ -173,7 +150,6 @@
url = {http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/pc/at/6183355_PC_AT_Technical_Reference_Mar86.pdf},
urldate = {2023-02-08},
year = {1986},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/PC_AT Technical Reference.pdf:PDF},
}
@Manual{80386,
@ -182,7 +158,6 @@
url = {https://bitsavers.org/components/intel/80386/230985-001_80386_Programmers_Reference_Manual_1986.pdf},
urldate = {2023-02-10},
year = {1986},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 80386 Manual.pdf:PDF},
}
@Misc{x86isa,
@ -263,8 +238,6 @@
urldate = {2023-02-26},
year = {1993},
note = {Rev 5},
abstract = {DATASHEET SEARCH, DATABOOK, COMPONENT, FREE DOWNLOAD SITE},
file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 8254 Datasheet.pdf:PDF},
}
@Comment{jabref-meta: databaseType:bibtex;}