Sync with BSuSP
This commit is contained in:
@ -1,7 +1,7 @@
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<div align="center">
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<img src="https://coconucos.cs.hhu.de/lehre/bigdata/resources/img/hhu-logo.svg" width=300>
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[](/../-/jobs/artifacts/main/file/thesis.pdf?job=latex)
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[](/../-/jobs/artifacts/master/file/document/thesis.pdf?job=latex)
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</div>
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# :notebook: Aufgabenbeschreibung
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@ -76,8 +76,7 @@ $ ./run.sh --bios true --file hhuOS.iso
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- `src/device/interrupt/apic/*`
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- `src/device/time/ApicTimer.*`
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- `src/device/cpu/Smp.*`
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- `src/device/cpu/smp.asm`
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- `src/device/cpu/smp_*`
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# Commit history
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@ -1,7 +1,9 @@
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\chapter{Figures}
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\label{ch:figures}
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\begin{figure}[h]
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\clearpage
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\begin{figure}[H]
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\centering
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\begin{subfigure}[b]{0.85\textwidth}
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\includesvg[width=1.0\linewidth]{diagrams/apic_enable_seq.svg}
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@ -10,7 +12,7 @@
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\label{fig:apicenable}
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\end{figure}
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\begin{figure}[h]
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\begin{figure}[H]
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\centering
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\begin{subfigure}[b]{0.85\textwidth}
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\includesvg[width=1.0\linewidth]{diagrams/apic_smp_enable_seq.svg}
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@ -38,7 +38,7 @@ Specifically, QEMU provides the current register state of all local and I/O APIC
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\end{itemize}
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Although hhuOS is developed mainly for learning purposes, every OS' core task remains to be the management of computer hardware.
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For this reason, this implementation was additionally tested on a \textquote{ThinkPad T60s} with an Intel \textquote{Core 2 Duo} processor.
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For this reason, this implementation was additionally tested on a \textquote{ThinkPad X60s} with an Intel \textquote{Core 2 Duo} processor.
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By providing internal status data through the virtual file system, implemented features (including booting additional APs) were verified on this very specific set of hardware.
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More specifically, information about detected and enabled local APICs and the I/O APIC, register values from the BSP's LVT and the REDTBL, the contents of the PIC's \textbf{\gls{imr}}, and the number of occurred interrupts by core (similar to \code{/proc/interrupts} in Linux~\autocite{linux}) are exposed on the path \code{/device/apic/}.
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@ -54,7 +54,7 @@ This way, the following things could be verified on real hardware:
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Interestingly, this was easier to verify on real hardware than in QEMU, because QEMU usually instantly crashes when interrupts are enabled on an AP beside the BSP\@.
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Also, redirecting the keyboard interrupt in QEMU significantly changes the behavior of any key press and renders the keyboard unusable.
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This is expected, as hhuOS' paging is not designed for multiple processors.
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On the ThinkPad T60s though, it was possible (surprisingly) to use the redirected keyboard interrupt to \code{cat} the \code{/device/apic/irqs} file to observe the interrupt statistics, which showed the keyboard interrupts indeed arriving at a different core than the BSP\@.
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On the ThinkPad X60s though, it was possible (surprisingly) to use the redirected keyboard interrupt to \code{cat} the \code{/device/apic/irqs} file to observe the interrupt statistics, which showed the keyboard interrupts indeed arriving at a different core than the BSP\@.
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After a certain time, the system crashes on the ThinkPad as well.}.
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\end{itemize}
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@ -6,9 +6,6 @@
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urldate = {2023-02-08},
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year = {1978},
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note = {Rev 3},
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comment = {Datasheet for Intel's Programmable Interrupt Controller},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 8259A Datasheet.pdf:PDF},
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keywords = {PIC},
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}
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@Manual{ia32,
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@ -18,9 +15,6 @@
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url = {https://cdrdv2.intel.com/v1/dl/getContent/671200},
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urldate = {2023-02-08},
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year = {2022},
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abstract = {The general manual for Intel's 32 bit and 64 bit architectures},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 64 and IA-32 Manual.pdf:PDF},
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keywords = {x86, Intel 64, Intel IA-32},
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}
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@Manual{ioapic,
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@ -30,9 +24,6 @@
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url = {https://pdos.csail.mit.edu/6.828/2017/readings/ia32/ioapic.pdf},
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urldate = {2023-02-08},
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year = {1996},
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comment = {Datasheet of Intel's external I/O APIC},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 82093AA Datasheet.pdf:PDF},
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keywords = {I/O APIC},
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}
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@Manual{acpi1,
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@ -43,7 +34,6 @@
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urldate = {2023-02-08},
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year = {1999},
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note = {Rev 1.0b},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/ACPI 1 Specification.pdf:PDF},
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}
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@Manual{acpi2,
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@ -54,7 +44,6 @@
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urldate = {2023-02-08},
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year = {2003},
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note = {Rev 2.0c},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/ACPI 2 Specification.pdf:PDF},
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}
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@Manual{acpi65,
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urldate = {2023-02-08},
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year = {2022},
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note = {Rev 6.5},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/ACPI 6_5 Specification.pdf:PDF},
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keywords = {ACPI Specification, UEFI},
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}
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@Manual{cpp20draft,
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urldate = {2023-02-08},
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year = {2020},
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note = {N4860},
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abstract = {C++ Draft International Standard},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/C++20 Standard Draft.pdf:PDF},
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}
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@Manual{c99draft,
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urldate = {2023-02-08},
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year = {1999},
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note = {N1256},
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abstract = {Programming languages - C},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/C99 Standard Draft.pdf:PDF},
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}
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@Manual{ich2,
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url = {https://www.intel.com/content/dam/doc/datasheet/82801ba-i-o-controller-hub-2-82801bam-i-o-controller-hub-2-mobile-datasheet.pdf},
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urldate = {2023-02-08},
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year = {2000},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel ICH2 Datasheet.pdf:PDF},
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}
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@Manual{ich5,
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urldate = {2023-02-08},
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year = {2003},
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note = {Rev 001},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel ICH5 Datasheet.pdf:PDF},
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}
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@Manual{mpspec,
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urldate = {2023-02-08},
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year = {1997},
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note = {Rev 1.4},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel MultiProcessor Specification.pdf:PDF},
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}
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@TechReport{msilatency,
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year = {2009},
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month = jan,
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type = {techreport},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel Reducing Interrupt Latency through the Use of MSIs Whitepaper.pdf:PDF},
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url = {https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf},
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}
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url = {https://www.scss.tcd.ie/~jones/CS4021/processor-identification-cpuid-instruction-note.pdf},
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urldate = {2023-02-08},
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year = {2012},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel CPUID Application Note.pdf:PDF},
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}
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@Misc{hhuos,
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urldate = {2023-02-08},
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year = {1998},
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note = {Rev 2.2},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/PCI 2_2 Specification.pdf:PDF},
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}
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@Manual{pcat,
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url = {http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/pc/at/6183355_PC_AT_Technical_Reference_Mar86.pdf},
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urldate = {2023-02-08},
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year = {1986},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/PC_AT Technical Reference.pdf:PDF},
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}
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@Manual{80386,
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url = {https://bitsavers.org/components/intel/80386/230985-001_80386_Programmers_Reference_Manual_1986.pdf},
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urldate = {2023-02-10},
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year = {1986},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 80386 Manual.pdf:PDF},
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}
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@Misc{x86isa,
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urldate = {2023-02-26},
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year = {1993},
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note = {Rev 5},
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abstract = {DATASHEET SEARCH, DATABOOK, COMPONENT, FREE DOWNLOAD SITE},
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file = {:/home/christoph/Notes/HHU/Bachelorarbeit/literature/Intel 8254 Datasheet.pdf:PDF},
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}
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@Comment{jabref-meta: databaseType:bibtex;}
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