Richard Hellwig f41247b143 gem5: don't count instruction fetch as mem access ...

Change-Id: I6ea9811c132ef7c235d5a03486ca08afc842b51f

2014-01-06 15:54:02 +01:00

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checker

Adding gem5 source to svn.

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inorder

Adding gem5 source to svn.

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nocpu

Adding gem5 source to svn.

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o3

gem5: codebase patched to compile with ag++

2013-05-16 15:35:28 +02:00

ozone

Adding gem5 source to svn.

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pred

Adding gem5 source to svn.

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simple

gem5: don't count instruction fetch as mem access

2014-01-06 15:54:02 +01:00

testers

Adding gem5 source to svn.

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trace

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activity.cc

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activity.hh

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base_dyn_inst_impl.hh

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base_dyn_inst.hh

Adding gem5 source to svn.

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base.cc

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base.hh

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BaseCPU.py

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CheckerCPU.py

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cpuevent.cc

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cpuevent.hh

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decode_cache.hh

Adding gem5 source to svn.

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dummy_checker_builder.cc

Adding gem5 source to svn.

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DummyChecker.py

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exec_context.hh

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exetrace.cc

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exetrace.hh

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ExeTracer.py

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func_unit.cc

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func_unit.hh

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FuncUnit.py

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inst_seq.hh

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inteltrace.cc

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inteltrace.hh

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IntelTrace.py

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intr_control.cc

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intr_control.hh

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IntrControl.py

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legiontrace.cc

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legiontrace.hh

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LegionTrace.py

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m5legion_interface.h

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nativetrace.cc

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nativetrace.hh

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NativeTrace.py

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op_class.hh

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pc_event.cc

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pc_event.hh

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profile.cc

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profile.hh

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quiesce_event.cc

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quiesce_event.hh

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SConscript

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simple_thread.cc

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simple_thread.hh

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smt.hh

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static_inst_fwd.hh

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static_inst.cc

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static_inst.hh

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thread_context.cc

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thread_context.hh

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thread_state.cc

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thread_state.hh

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timebuf.hh

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translation.hh

Adding gem5 source to svn.

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