Richard Hellwig f41247b143 gem5: don't count instruction fetch as mem access ...

Change-Id: I6ea9811c132ef7c235d5a03486ca08afc842b51f

2014-01-06 15:54:02 +01:00

..

arch

gem5: codebase patched to compile with ag++

2013-05-16 15:35:28 +02:00

base

gem5: codebase patched to compile with ag++

2013-05-16 15:35:28 +02:00

cpu

gem5: don't count instruction fetch as mem access

2014-01-06 15:54:02 +01:00

dev

- Added signaling of trap situations needed in the weather-monitor to gem5.

2013-01-30 23:59:24 +00:00

doxygen

Adding gem5 source to svn.

2012-10-24 19:18:57 +00:00

kern

Adding gem5 source to svn.

2012-10-24 19:18:57 +00:00

mem

gem5: codebase patched to compile with ag++

2013-05-16 15:35:28 +02:00

python

gem5: codebase patched to compile with ag++

2013-05-16 15:35:28 +02:00

sim

gem5: restore works now

2013-11-13 17:15:19 +01:00

unittest

Adding gem5 source to svn.

2012-10-24 19:18:57 +00:00

Doxyfile

Adding gem5 source to svn.

2012-10-24 19:18:57 +00:00

SConscript

gem5 buildsys: compiler flag fixed due to newer gcc version

2013-07-31 17:08:14 +02:00