The build system now allows incremental gem5 builds. Unfortunately,
the current solution always requires re-linking the executable.
Without the enforcement of re-linking, the fail code will be rebuilt
but not linked into gem5.
The number of cores for building gem5 is derived from /proc/cpuinfo.
As before, only the gem5.debug configuration is supported.
Change-Id: Ib13b15d1ecd62196eb251e0fd00953f4eb052feb
This changes allows us to compile the gem5 simulator with ag++. It
was tested with ag++ v0.8, built Apr 18 2013. Most of the changes
are preprocessor directives like #ifndef __puma which have been
inserted into the gem5 code. Unfortunately, a python script and a
SWIG input file have been patched, too.
Additionally, the CMake file has been updated. A single call to
"make" now invokes the ag++ (instead of the g++) compiler front
end. The new CMake target "gem5-allclean" should be used to clean
the current project when building FailGem5. In addition to cleaning
the Fail build directory, it also invokes "scons -c" in the gem5
build directory; that is, gem5 is cleaned as well.
Change-Id: I20a92f025f34f626b81e30f2c873baeba189f83b
Now, the gem5 implementation equals the Bochs variant. Note that its
necessary to enable CONFIG_EVENTS_BREAKPOINTS_RANGE in order to use
range breakpoints.
In addition, gem5 distinguishes between macro- and microops. With the
new implemenation, onBreakpoint is only called when a macroop changes.
Change-Id: Ib86d1802fc70c20d22ca1a1ece0e8d1221b2e7db
- Gem5 now has two different implementation for breakpoints.
- If only BPSingleListener are used, gem5 Breakpoints are used
- If BPRangeListener are used, gem5 calls onBreakpoint() in every simulated instruction
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2003 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
- The register manager is gone. It's functionality is now encapsulated in the
CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
to the CPU state (including registers) and architecture details. The
correspondig objects for the CPUs inside the simulator can be accessed
through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
should fire. The default NULL is used as wildcard for all aviable CPUs. The
events respectively got a ConcreteCPU* member to indicate which CPU really
fired the event.
- For the server, there is CPUArchitecture to access the architecture details.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
- FailGem5Device is gone.
- There are now changes directly made to the gem5 source.
- Gem5Connector is a helper class that is compiled inside the gem5 context to workaround problems with gem5 header in fail.
Things that are working:
- BPSingleListener
- MemAccessListener
- Save and restore simulator state
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1820 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
