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hsc-simple: modifications due to architecure changes in r1966.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1973 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
2012-12-12 13:08:12 +00:00
parent 4189871920
commit fb4ba0b104
1 changed files with 3 additions and 2 deletions
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5
src/experiments/hsc-simple/experiment.cc
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@ -39,7 +39,8 @@ bool HSCSimpleExperiment::run()
simulator.addListenerAndResume(&breakpoint); simulator.addListenerAndResume(&breakpoint);
log << "injecting hellish fault" << endl; log << "injecting hellish fault" << endl;
// RID_CAX is the RAX register in 64 bit mode and EAX in 32 bit mode: // RID_CAX is the RAX register in 64 bit mode and EAX in 32 bit mode:
simulator.getRegisterManager().getRegister(RID_CAX)->setData(666); Register* reg = simulator.getCPU(0).getRegister(RID_CAX);
simulator.getCPU(0).setRegisterContent(reg, 666);
log << "waiting for last main() instruction" << endl; log << "waiting for last main() instruction" << endl;
breakpoint.setWatchInstructionPointer(0x3c92); breakpoint.setWatchInstructionPointer(0x3c92);
simulator.addListenerAndResume(&breakpoint); simulator.addListenerAndResume(&breakpoint);
@ -49,6 +50,6 @@ bool HSCSimpleExperiment::run()
simulator.addListenerAndResume(&breakpoint); simulator.addListenerAndResume(&breakpoint);
#endif #endif
simulator.clearListeners(this); simulator.terminate();
return true; return true;
} }