gem5: codebase patched to compile with ag++

This changes allows us to compile the gem5 simulator with ag++. It
was tested with ag++ v0.8, built Apr 18 2013. Most of the changes
are preprocessor directives like #ifndef __puma which have been
inserted into the gem5 code. Unfortunately, a python script and a
SWIG input file have been patched, too.
Additionally, the CMake file has been updated. A single call to
"make" now invokes the ag++ (instead of the g++) compiler front
end. The new CMake target "gem5-allclean" should be used to clean
the current project when building FailGem5. In addition to cleaning
the Fail build directory, it also invokes "scons -c" in the gem5
build directory; that is, gem5 is cleaned as well.

Change-Id: I20a92f025f34f626b81e30f2c873baeba189f83b

simulators/gem5/src/cpu/o3/commit_impl.hh

@@ -355,6 +355,8 @@ DefaultCommit<Impl>::setROB(ROB *rob_ptr)
     rob = rob_ptr;
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template <class Impl>
 void
 DefaultCommit<Impl>::initStage()
@@ -1342,6 +1344,8 @@ DefaultCommit<Impl>::markCompletedInsts()
     }
 }
 
+#endif // !__puma (DanceOS)
+
 template <class Impl>
 bool
 DefaultCommit<Impl>::robDoneSquashing()

simulators/gem5/src/cpu/o3/decode_impl.hh

@@ -214,6 +214,8 @@ DefaultDecode<Impl>::checkStall(ThreadID tid) const
     return ret_val;
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template<class Impl>
 inline bool
 DefaultDecode<Impl>::fetchInstsValid()
@@ -759,3 +761,5 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
         wroteToTimeBuffer = true;
     }
 }
+
+#endif // !__puma (DanceOS)

simulators/gem5/src/cpu/o3/fetch_impl.hh

@@ -826,6 +826,8 @@ DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
     cpu->removeInstsNotInROB(tid);
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template <class Impl>
 void
 DefaultFetch<Impl>::tick()
@@ -1514,6 +1516,8 @@ DefaultFetch<Impl>::lsqCount()
     return InvalidThreadID;
 }
 
+#endif // !__puma (DanceOS)
+
 template<class Impl>
 ThreadID
 DefaultFetch<Impl>::branchCount()

simulators/gem5/src/cpu/o3/iew_impl.hh

@@ -281,6 +281,8 @@ DefaultIEW<Impl>::regStats()
     wbRate = writebackCount / cpu->numCycles;
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template<class Impl>
 void
 DefaultIEW<Impl>::initStage()
@@ -1668,3 +1670,5 @@ DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
         }
     }
 }
+
+#endif // !__puma (DanceOS)

simulators/gem5/src/cpu/o3/inst_queue_impl.hh

@@ -1116,6 +1116,8 @@ InstructionQueue<Impl>::violation(DynInstPtr &store,
     memDepUnit[store->threadNumber].violation(store, faulting_load);
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template <class Impl>
 void
 InstructionQueue<Impl>::squash(ThreadID tid)
@@ -1136,6 +1138,8 @@ InstructionQueue<Impl>::squash(ThreadID tid)
     memDepUnit[tid].squash(squashedSeqNum[tid], tid);
 }
 
+#endif // !__puma (DanceOS)
+
 template <class Impl>
 void
 InstructionQueue<Impl>::doSquash(ThreadID tid)

simulators/gem5/src/cpu/o3/rename_impl.hh

@@ -335,6 +335,8 @@ DefaultRename<Impl>::takeOverFrom()
     }
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template <class Impl>
 void
 DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
@@ -1338,6 +1340,8 @@ DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
     return false;
 }
 
+#endif // !__puma (DanceOS)
+
 template<class Impl>
 void
 DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)