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Bugfixes for aspect headers due to architecure-related changes.

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Now, each aspect calls it's corresponding event headler by providing the new CPU object pointer as well.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2007 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
2013-01-17 13:41:11 +00:00
parent 214bb36b47
commit edf44aec28
7 changed files with 50 additions and 28 deletions
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11
src/core/sal/bochs/Breakpoints.ah
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@ -24,15 +24,8 @@ aspect Breakpoints {
bxInstruction_c* pInstr = *(tjp->arg<1>()); bxInstruction_c* pInstr = *(tjp->arg<1>());
// Detect the CPU that triggered the change: // Detect the CPU that triggered the change:
unsigned i = 0; fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(pThis);
#if BX_SUPPORT_SMP // FIXME: Slice ConcreteCPU object reference into BOCHS_CPU -> simplified
for (; i < BX_SMP_PROCESSORS; i++) {
if (BX_CPU_C[i] == pThis) // cmp this ptr with all possible CPU objects
break; // index "i" found! -> stop!
}
#endif
fail::ConcreteCPU& triggerCPU = fail::simulator.getCPU(i);
// FIXME: slice ConcreteCPU object reference into BOCHS_CPU -> simplified
// Report this event to the Bochs controller: // Report this event to the Bochs controller:
fail::simulator.updateBPEventInfo(pThis, pInstr); fail::simulator.updateBPEventInfo(pThis, pInstr);

9
src/core/sal/bochs/IOPortCom.ah
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@ -10,7 +10,6 @@
#include "cpu/cpu.h" #include "cpu/cpu.h"
#include "../SALInst.hpp" #include "../SALInst.hpp"
#include "BochsHelpers.hpp" #include "BochsHelpers.hpp"
// TODO: ATM only capturing bytewise output (most common, I suppose) // TODO: ATM only capturing bytewise output (most common, I suppose)
@ -22,7 +21,10 @@ aspect IOPortCom {
{ {
unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number
unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data
fail::simulator.onIOPort(rAL, rDX, true);
// Detect the CPU that triggered the change:
fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onIOPort(&triggerCPU, rAL, rDX, true);
} }
pointcut inInstruction() = "% ...::bx_cpu_c::IN_ALDX(...)"; pointcut inInstruction() = "% ...::bx_cpu_c::IN_ALDX(...)";
@ -31,7 +33,8 @@ aspect IOPortCom {
{ {
unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number
unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data
fail::simulator.onIOPort(rAL, rDX, false); fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onIOPort(&triggerCPU, rAL, rDX, false);
} }
}; };

7
src/core/sal/bochs/Interrupt.ah
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@ -26,12 +26,15 @@ aspect Interrupt {
// - BX_SOFTWARE_EXCEPTION = 6 // - BX_SOFTWARE_EXCEPTION = 6
// Only the first and the second types are relevant for this aspect. // Only the first and the second types are relevant for this aspect.
// Detect the CPU that triggered the change:
fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
unsigned vector = *(tjp->arg<0>()); unsigned vector = *(tjp->arg<0>());
unsigned type = *(tjp->arg<1>()); unsigned type = *(tjp->arg<1>());
if (type == BX_EXTERNAL_INTERRUPT) if (type == BX_EXTERNAL_INTERRUPT)
fail::simulator.onInterrupt(vector, false); fail::simulator.onInterrupt(&triggerCPU, vector, false);
else if (type == BX_NMI) else if (type == BX_NMI)
fail::simulator.onInterrupt(vector, true); fail::simulator.onInterrupt(&triggerCPU, vector, true);
} }
}; };

8
src/core/sal/bochs/InterruptSuppression.ah
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@ -15,11 +15,15 @@ aspect InterruptSuppression {
pointcut interrupt_method() = "void bx_cpu_c::interrupt(...)"; pointcut interrupt_method() = "void bx_cpu_c::interrupt(...)";
advice execution (interrupt_method()) : around () advice execution (interrupt_method()) : around ()
{ {
// Detect the CPU that triggered the change:
fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
unsigned vector = *(tjp->arg<0>()); unsigned vector = *(tjp->arg<0>());
if (!fail::simulator.isSuppressedInterrupt(vector)) { if (!triggerCPU.isSuppressedInterrupt(vector)) {
tjp->proceed(); tjp->proceed();
} }
// else: do not process the interrupt
} }
}; };

11
src/core/sal/bochs/Jump.ah
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@ -14,6 +14,7 @@
#include "bochs.h" #include "bochs.h"
#include "../SALInst.hpp" #include "../SALInst.hpp"
#include "BochsHelpers.hpp"
// FIXME: This seems (partial) deprecated/incomplete as well... // FIXME: This seems (partial) deprecated/incomplete as well...
@ -61,7 +62,10 @@ aspect Jump {
advice execution (defJumpInstructions()) : around() advice execution (defJumpInstructions()) : around()
{ {
bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object
fail::simulator.onJump(true, pInstr->getIaOpcode());
// Detect the CPU that triggered the change:
fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onJump(&triggerCPU, true, pInstr->getIaOpcode());
/* /*
JoinPoint::That* pThis = tjp->that(); JoinPoint::That* pThis = tjp->that();
if(pThis == NULL) if(pThis == NULL)
@ -110,7 +114,10 @@ aspect Jump {
advice execution (regJumpInstructions()) : around () advice execution (regJumpInstructions()) : around ()
{ {
bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object bxInstruction_c* pInstr = *(tjp->arg<0>()); // bxInstruction_c-object
fail::simulator.onJump(false, pInstr->getIaOpcode());
// Detect the CPU that triggered the change:
fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onJump(&triggerCPU, false, pInstr->getIaOpcode());
/* /*
JoinPoint::That* pThis = tjp->that(); JoinPoint::That* pThis = tjp->that();

27
src/core/sal/bochs/MemAccess.ah
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@ -63,14 +63,16 @@ aspect MemAccess {
#ifdef CONFIG_EVENT_MEMWRITE #ifdef CONFIG_EVENT_MEMWRITE
advice execution (write_methods()) : after () advice execution (write_methods()) : after ()
{ {
fail::simulator.onMemoryAccess( fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onMemoryAccess(&triggerCPU,
*(tjp->arg<1>()), sizeof(*(tjp->arg<2>())), true, *(tjp->arg<1>()), sizeof(*(tjp->arg<2>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
advice execution (write_methods_RMW()) : after () advice execution (write_methods_RMW()) : after ()
{ {
fail::simulator.onMemoryAccess( fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onMemoryAccess(&triggerCPU,
rmw_address, sizeof(*(tjp->arg<0>())), true, rmw_address, sizeof(*(tjp->arg<0>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
@ -79,7 +81,8 @@ aspect MemAccess {
{ {
//std::cerr << "WOOOOOT write_methods_new_stack" << std::endl; //std::cerr << "WOOOOOT write_methods_new_stack" << std::endl;
// TODO: Log-level? // TODO: Log-level?
fail::simulator.onMemoryAccess( fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onMemoryAccess(&triggerCPU,
*(tjp->arg<1>()), sizeof(*(tjp->arg<3>())), true, *(tjp->arg<1>()), sizeof(*(tjp->arg<3>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
@ -88,7 +91,8 @@ aspect MemAccess {
{ {
//std::cerr << "WOOOOOT write_methods_new_stack_64" << std::endl; //std::cerr << "WOOOOOT write_methods_new_stack_64" << std::endl;
// TODO: Log-level? // TODO: Log-level?
fail::simulator.onMemoryAccess( fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onMemoryAccess(&triggerCPU,
*(tjp->arg<0>()), sizeof(*(tjp->arg<2>())), true, *(tjp->arg<0>()), sizeof(*(tjp->arg<2>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
@ -100,7 +104,8 @@ aspect MemAccess {
// memory (e.g., to read vectors from the interrupt vector // memory (e.g., to read vectors from the interrupt vector
// table). // table).
/* /*
fail::simulator.onMemoryAccess( fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onMemoryAccess(&triggerCPU,
*(tjp->arg<0>()), sizeof(*(tjp->arg<1>())), true, *(tjp->arg<0>()), sizeof(*(tjp->arg<1>())), true,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
*/ */
@ -116,14 +121,16 @@ aspect MemAccess {
#ifdef CONFIG_EVENT_MEMREAD #ifdef CONFIG_EVENT_MEMREAD
advice execution (read_methods()) : before () advice execution (read_methods()) : before ()
{ {
fail::simulator.onMemoryAccess( fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onMemoryAccess(&triggerCPU,
*(tjp->arg<1>()), sizeof(*(tjp->result())), false, *(tjp->arg<1>()), sizeof(*(tjp->result())), false,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
advice execution (read_methods_dqword()) : before () advice execution (read_methods_dqword()) : before ()
{ {
fail::simulator.onMemoryAccess( fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onMemoryAccess(&triggerCPU,
*(tjp->arg<1>()), 16, false, *(tjp->arg<1>()), 16, false,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
} }
@ -135,7 +142,8 @@ aspect MemAccess {
rmw_address = *(tjp->arg<1>()); rmw_address = *(tjp->arg<1>());
#endif #endif
#ifdef CONFIG_EVENT_MEMREAD #ifdef CONFIG_EVENT_MEMREAD
fail::simulator.onMemoryAccess( fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onMemoryAccess(&triggerCPU,
*(tjp->arg<1>()), sizeof(*(tjp->result())), false, *(tjp->arg<1>()), sizeof(*(tjp->result())), false,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
#endif #endif
@ -149,7 +157,8 @@ aspect MemAccess {
// memory (e.g., to read vectors from the interrupt vector // memory (e.g., to read vectors from the interrupt vector
// table). // table).
/* /*
fail::simulator.onMemoryAccess( fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onMemoryAccess(&triggerCPU,
*(tjp->arg<0>()), sizeof(*(tjp->result())), false, *(tjp->arg<0>()), sizeof(*(tjp->result())), false,
getCPU(tjp->that())->prev_rip); getCPU(tjp->that())->prev_rip);
*/ */

5
src/core/sal/bochs/Trap.ah
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@ -10,13 +10,16 @@
#include "cpu/cpu.h" #include "cpu/cpu.h"
#include "../SALInst.hpp" #include "../SALInst.hpp"
#include "BochsHelpers.hpp"
aspect Trap { aspect Trap {
pointcut exception_method() = "void bx_cpu_c::exception(...)"; pointcut exception_method() = "void bx_cpu_c::exception(...)";
advice execution (exception_method()) : before () advice execution (exception_method()) : before ()
{ {
fail::simulator.onTrap(*(tjp->arg<0>())); // Detect the CPU that triggered the change:
fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onTrap(&triggerCPU, *(tjp->arg<0>()));
// TODO: There are some different types of exceptions at cpu.h (line 265-281) // TODO: There are some different types of exceptions at cpu.h (line 265-281)
// Which kind of traps are these types? // Which kind of traps are these types?
} }