christoph/fail
1
Fork 0
Code Releases Activity

sal/bochs: catch all I/O instructions

Browse Source 
Up to now, the IOPortListener only caught invocations of INB/OUTB with
the port number in DX and 8-bit input/output (from/to AL), but none of
the various other methods to access the I/O port range (e.g., by 8-bit
immediate port numbers).  This change is supposed to catch all other
cases, too.

Change-Id: I1180cd9c1d59df600067739817adab684b18a608
This commit is contained in:
Horst Schirmeier
2014-07-02 16:18:50 +02:00
parent a198eda8c8
commit c2eb718886
1 changed files with 17 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
src/core/sal/bochs/IOPortCom.ah
View File

@ -12,29 +12,33 @@
#include "../SALInst.hpp"
#include "BochsHelpers.hpp"
// TODO: ATM only capturing bytewise output (most common, I suppose)
// FIXME ATM only capturing the first byte of a multi-byte in/out
aspect IOPortCom {
pointcut outInstruction() = "% ...::bx_cpu_c::OUT_DXAL(...)";
pointcut devices_outp() = "% ...::bx_devices_c::outp(...)";
advice execution (outInstruction()) : after ()
advice call (devices_outp()) && within ("...::bx_cpu_c") : before ()
{
unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number
unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data
// Detect the CPU that triggered the change:
unsigned port = *(tjp->arg<0>());
unsigned data = *(tjp->arg<1>());
// detect the CPU that triggered the access
fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onIOPort(&triggerCPU, rAL, rDX, true);
// forward to SimulatorController
fail::simulator.onIOPort(&triggerCPU, data, port, true);
}
pointcut inInstruction() = "% ...::bx_cpu_c::IN_ALDX(...)";
pointcut devices_inp() = "% ...::bx_devices_c::inp(...)";
advice execution (inInstruction()) : after ()
advice call (devices_inp()) && within ("...::bx_cpu_c") : after ()
{
unsigned rDX = getCPU(tjp->that())->gen_reg[2].word.rx; // port number
unsigned char rAL = getCPU(tjp->that())->gen_reg[0].word.byte.rl; // data
unsigned port = *(tjp->arg<0>());
unsigned data = *(tjp->result());
// detect the CPU that triggered the access
fail::ConcreteCPU& triggerCPU = fail::simulator.detectCPU(getCPU(tjp->that()));
fail::simulator.onIOPort(&triggerCPU, rAL, rDX, false);
// forward to SimulatorController
fail::simulator.onIOPort(&triggerCPU, data, port, false);
}
};