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T32SIM: Integrating Tracing feature of the T32SIM.

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After each simulator break, T32Tracer retrieves the latest (16)
trace records from the T32. Memory address and value can now
be evaluated easily from the trace record.

TODO:Nevertheless we still have to traverse the trace to
find the instruction causing the access.
This commit is contained in:
Martin Hoffmann
2013-03-21 17:59:21 +01:00
parent 4e8098a636
commit b8e706b1a5
17 changed files with 270 additions and 26 deletions
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1
debuggers/t32/sim/CMakeLists.txt
View File

@ -1,4 +1,3 @@
include_directories(include)
add_subdirectory(${T32_ARCHITECTURE})
add_subdirectory(memlogger)

41
debuggers/t32/sim/memlogger/memlogger.c
View File

@ -9,21 +9,31 @@
typedef struct
{
simulWord infoBase;
int bustype;
int data;
}
MemLog_t;
static int SIMULAPI readCB(simulProcessor processor, simulCallbackStruct * cbs, simulPtr private)
{
// simulWord address = cbs->x.bus.address;
simulWord address = cbs->x.bus.address;
MemLog_t * memlog = (MemLog_t*)private;
cbs->x.bus.data = memlog->data;
//int width = cbs->x.bus.width;
SIMUL_Printf(processor, "MEM Read *0x%x - 0x%x\n", cbs->x.bus.address, memlog->data);
simulWord width = cbs->x.bus.width;
SIMUL_Printf(processor, "MEM Read *0x%x - 0x%x\n", address, memlog->data);
simulWord data = memlog->data;
simulWord writeAccess = 0;
simulWord iadr = memlog->infoBase;
SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &address);
iadr += 4;
SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &data);
iadr += 4;
SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &width);
iadr += 4;
SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &writeAccess);
return SIMUL_MEMORY_OK;
}
@ -31,11 +41,23 @@ static int SIMULAPI readCB(simulProcessor processor, simulCallbackStruct * cbs,
static int SIMULAPI writeCB(simulProcessor processor, simulCallbackStruct * cbs, simulPtr private)
{
simulWord data = cbs->x.bus.data;
//simulWord address = cbs->x.bus.address;
simulWord address = cbs->x.bus.address;
MemLog_t * memlog = (MemLog_t*)private;
memlog->data = cbs->x.bus.data;
//int width = cbs->x.bus.width;
SIMUL_Printf(processor, "MEM Write *0x%x - 0x%x\n", cbs->x.bus.address, data);
simulWord width = cbs->x.bus.width;
SIMUL_Printf(processor, "MEM Write *0x%x - 0x%x\n", address, data);
simulWord writeAccess = 1;
simulWord iadr = memlog->infoBase;
SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &address);
iadr += 4;
SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &data);
iadr += 4;
SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &width);
iadr += 4;
SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &writeAccess);
return SIMUL_MEMORY_OK;
}
@ -66,6 +88,7 @@ int SIMULAPI SIMUL_Init(simulProcessor processor, simulCallbackStruct * cbs)
// return SIMUL_INIT_FAIL;
// }
pmemlog->bustype = cbs->x.init.argpbustype[1];
pmemlog->infoBase = 0x60000000; // placed at "external RAM"
simulWord from, to;
from = 0x20002074;