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coding-style++, gem5 code doc added

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2083 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
2013-02-14 14:45:18 +00:00
parent c8a9039f36
commit accfba8237
5 changed files with 56 additions and 14 deletions
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11
src/core/sal/gem5/Gem5ArmCPU.cc
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@ -9,15 +9,11 @@ regdata_t Gem5ArmCPU::getRegisterContent(Register* reg)
if (reg->getIndex() == 15) {
return m_System->getThreadContext(m_Id)->pcState().pc();
}
return m_System->getThreadContext(m_Id)->readIntReg(reg->getIndex());
case RT_FP:
return m_System->getThreadContext(m_Id)->readFloatReg(reg->getIndex());
case RT_ST:
return m_System->getThreadContext(m_Id)->readMiscReg(reg->getIndex());
case RT_IP:
return m_System->getThreadContext(m_Id)->pcState().pc();
}
@ -32,15 +28,12 @@ void Gem5ArmCPU::setRegisterContent(Register* reg, regdata_t value)
switch (reg->getType()) {
case RT_GP:
m_System->getThreadContext(m_Id)->setIntReg(reg->getIndex(), value);
break;
break;
case RT_FP:
m_System->getThreadContext(m_Id)->setFloatReg(reg->getIndex(), value);
break;
break;
case RT_ST:
return m_System->getThreadContext(m_Id)->setMiscReg(reg->getIndex(), value);
case RT_IP:
return setRegisterContent(getRegister(RI_IP), value);
}