diff --git a/src/core/sal/Register.hpp b/src/core/sal/Register.hpp
index 28ce5988..f788a2a8 100644
--- a/src/core/sal/Register.hpp
+++ b/src/core/sal/Register.hpp
@@ -161,6 +161,7 @@ public:
 	 */
 	virtual Register* first() { return getRegister(0); }
 };
+
 } // end-of-namespace: fail
 
 #endif // __REGISTER_HPP__
diff --git a/src/core/sal/arm/Architecture.hpp b/src/core/sal/arm/Architecture.hpp
index 3b4ed44f..d80d142e 100644
--- a/src/core/sal/arm/Architecture.hpp
+++ b/src/core/sal/arm/Architecture.hpp
@@ -21,7 +21,8 @@ private:
 
 /**
  * \enum GPRegIndex
- * TODO.
+ * Defines the general purpose (GP) register identifier for the ARM
+ * plattform. Some of them are just aliases.
  */
 enum GPRegIndex {
 	RI_R0,
diff --git a/src/core/sal/arm/CPUState.hpp b/src/core/sal/arm/CPUState.hpp
index 11d59351..e8d6a018 100644
--- a/src/core/sal/arm/CPUState.hpp
+++ b/src/core/sal/arm/CPUState.hpp
@@ -6,6 +6,11 @@
 
 namespace fail {
 
+/**
+ * \class ArmCPUState
+ * This class represents the current state of a ARM based CPU. A final CPU class
+ * need to implement \c ArmCPUState and \c ArmArchitecture.
+ */
 class ArmCPUState : public CPUState {
 public:
 	virtual regdata_t getRegisterContent(Register* reg) = 0;
diff --git a/src/core/sal/gem5/Gem5ArmCPU.cc b/src/core/sal/gem5/Gem5ArmCPU.cc
index c457539b..af86b7f0 100644
--- a/src/core/sal/gem5/Gem5ArmCPU.cc
+++ b/src/core/sal/gem5/Gem5ArmCPU.cc
@@ -9,15 +9,11 @@ regdata_t Gem5ArmCPU::getRegisterContent(Register* reg)
 		if (reg->getIndex() == 15) {
 			return m_System->getThreadContext(m_Id)->pcState().pc();
 		}
-			
 		return m_System->getThreadContext(m_Id)->readIntReg(reg->getIndex());
-			
 	case RT_FP:
 		return m_System->getThreadContext(m_Id)->readFloatReg(reg->getIndex());
-	
 	case RT_ST:
 		return m_System->getThreadContext(m_Id)->readMiscReg(reg->getIndex());
-
 	case RT_IP:
 		return m_System->getThreadContext(m_Id)->pcState().pc();
 	}
@@ -32,15 +28,12 @@ void Gem5ArmCPU::setRegisterContent(Register* reg, regdata_t value)
 	switch (reg->getType()) {
 	case RT_GP:
 		m_System->getThreadContext(m_Id)->setIntReg(reg->getIndex(), value);
-	break;
-
+		break;
 	case RT_FP:
 		m_System->getThreadContext(m_Id)->setFloatReg(reg->getIndex(), value);
-	break;
-
+		break;
 	case RT_ST:
 		return m_System->getThreadContext(m_Id)->setMiscReg(reg->getIndex(), value);
-
 	case RT_IP:
 		return setRegisterContent(getRegister(RI_IP), value);
 	}
diff --git a/src/core/sal/gem5/Gem5ArmCPU.hpp b/src/core/sal/gem5/Gem5ArmCPU.hpp
index 773e4f9e..583787df 100644
--- a/src/core/sal/gem5/Gem5ArmCPU.hpp
+++ b/src/core/sal/gem5/Gem5ArmCPU.hpp
@@ -8,24 +8,66 @@
 
 namespace fail {
 
+/**
+ * \class Gem5ArmCPU
+ * 
+ * \c Gem5ArmCPU is the concrete CPU implementation for the gem5 ARM simulator. It
+ * implements the CPU interfaces \c ArmArchitecture and \c ArmCPUState.
+ * \c ArmArchitecture refers to architectural information (e.g. register \a count)
+ * while \c ArmCPUState encapsulates the CPU state (e.g. register \a content).
+ */
 class Gem5ArmCPU : public ArmArchitecture, public ArmCPUState {
 public:
-	// TODO: comments
+	/**
+	 * Creates a new gem5 CPU for ARM based targets.
+	 * @param id the unique ID of the CPU to be created (the first CPU0 has ID 0)
+	 * @param system the gem5 system object
+	 */
 	Gem5ArmCPU(unsigned int id, System* system) : m_Id(id), m_System(system) { }
+	/**
+	 * Retrieves the register content from the current gem5 CPU.
+	 * @param reg the destination register whose content should be retrieved
+	 * @return the content of register \c reg
+	 */
 	regdata_t getRegisterContent(Register* reg);
+	/**
+	 * Sets the register content for the  \a current gem5 CPU.
+	 * @param reg the (initialized) register object whose content should be set
+	 * @param value the new content of the register \c reg
+	 */
 	void setRegisterContent(Register* reg, regdata_t value);
+	/**
+	 * Retrieves the current instruction pointer (IP aka program counter, PC for short)
+	 * for the current CPU \c this.
+	 * @return the current instruction ptr address
+	 */
 
 	address_t getInstructionPointer();
 	address_t getStackPointer();
 	address_t getLinkRegister();
 
 	unsigned int getId() { return m_Id; }
+	/**
+	 * Retrieves the current stack pointer for the current CPU \c this.
+	 * @return the current stack ptr address
+	 */
+	/**
+	 * Retrieves the link register (return address when a function returns) for
+	 * the current CPU \c this. See
+	 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/ch02s08s01.html
+	 * for further information.
+	 * @return the current link register address
+	 */
+	/**
+	 * Returns the ID of the current CPU.
+	 * @return the unique ID of \c this CPU object
+	 */
 private:
-	unsigned int m_Id;
-	System* m_System;
+	unsigned int m_Id; //!< the unique ID of this CPU
+	System* m_System; //!< the gem5 system object
 };
 
-typedef Gem5ArmCPU ConcreteCPU;
+typedef Gem5ArmCPU ConcreteCPU; //!< the concrete CPU type for ARM + gem5
 
 } // end-of-namespace: fail