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- Added signaling of trap situations needed in the weather-monitor to gem5.

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- Fixed setting of instruction address for simulator.onMemoryAccess() calls.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2025 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2013-01-30 23:59:24 +00:00
parent 640f5436cc
commit 9c62e4a7f2
5 changed files with 61 additions and 9 deletions
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35
simulators/gem5/src/cpu/simple/atomic.cc
View File

@ -289,12 +289,20 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
}
dcache_access = true;
// FAIL*
#ifdef CONFIG_EVENT_TRAP
if(pkt.isError()) {
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onTrap(cpu, 0);
}
#endif
assert(!pkt.isError());
// FAIL*
#ifdef CONFIG_EVENT_MEMREAD
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), false, 0);
fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), false, instAddr());
#endif
if (req->isLLSC()) {
@ -396,12 +404,21 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
dcache_latency += dcachePort.sendAtomic(&pkt);
}
dcache_access = true;
// FAIL*
#ifdef CONFIG_EVENT_TRAP
if(pkt.isError()) {
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onTrap(cpu, 0);
}
#endif
assert(!pkt.isError());
// FAIL*
#ifdef CONFIG_EVENT_MEMWRITE
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), true, 0);
fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), true, instAddr());
#endif
if (req->isSwap()) {
@ -496,11 +513,21 @@ AtomicSimpleCPU::tick()
else
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
assert(!ifetch_pkt.isError());
// FAIL*
#ifdef CONFIG_EVENT_TRAP
if(ifetch_pkt.isError())
{
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onTrap(cpu, 0);
}
#endif
assert(!ifetch_pkt.isError());
// FAIL*
#ifdef CONFIG_EVENT_MEMREAD
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onMemoryAccess(cpu, ifetch_pkt.getAddr(), ifetch_pkt.getSize(), false, 0);
fail::simulator.onMemoryAccess(cpu, ifetch_pkt.getAddr(), ifetch_pkt.getSize(), false, instAddr());
#endif
// ifetch_req is initialized to read the instruction directly

12
simulators/gem5/src/dev/arm/pl011.cc
View File

@ -51,6 +51,10 @@
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"
#include "config/FailConfig.hpp"
#include "sal/SALInst.hpp"
Pl011::Pl011(const Params *p)
: Uart(p), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), imsc(0),
rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic),
@ -180,8 +184,14 @@ Pl011::write(PacketPtr pkt)
switch (daddr) {
case UART_DR:
if ((data & 0xFF) == 0x04 && endOnEOT)
if ((data & 0xFF) == 0x04 && endOnEOT) {
// FAIL*
#ifdef CONFIG_EVENT_TRAP
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0);
fail::simulator.onTrap(cpu, 0);
#endif
exitSimLoop("UART received EOT", 0);
}
term->out(data & 0xFF);

12
simulators/gem5/src/dev/isa_fake.cc
View File

@ -39,6 +39,9 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
#include "config/FailConfig.hpp"
#include "sal/SALInst.hpp"
using namespace std;
IsaFake::IsaFake(Params *p)
@ -113,7 +116,14 @@ IsaFake::write(PacketPtr pkt)
data = pkt->get<uint8_t>();
break;
default:
panic("invalid access size!\n");
// FAIL*
#ifdef CONFIG_EVENT_TRAP
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0);
fail::simulator.onTrap(cpu, 0);
#endif
panic("invalid access size!\n");
}
warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
name(), pkt->getAddr(), pkt->getSize(), data);

3
simulators/gem5/src/mem/abstract_mem.cc
View File

@ -62,9 +62,6 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
#include "config/FailConfig.hpp"
#include "sal/SALInst.hpp"
using namespace std;
AbstractMemory::AbstractMemory(const Params *p) :

8
simulators/gem5/src/mem/bus.cc
View File

@ -53,6 +53,9 @@
#include "debug/BusAddrRanges.hh"
#include "mem/bus.hh"
#include "config/FailConfig.hpp"
#include "sal/SALInst.hpp"
BaseBus::BaseBus(const BaseBusParams *p)
: MemObject(p), clock(p->clock),
headerCycles(p->header_cycles), width(p->width), tickNextIdle(0),
@ -291,6 +294,11 @@ BaseBus::findPort(Addr addr)
// we should use the range for the default port and it did not
// match, or the default port is not set
// FAIL*
#ifdef CONFIG_EVENT_TRAP
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0);
fail::simulator.onTrap(cpu, 0);
#endif
fatal("Unable to find destination for addr %#llx on bus %s\n", addr,
name());
}