diff --git a/simulators/gem5/src/cpu/simple/atomic.cc b/simulators/gem5/src/cpu/simple/atomic.cc
index 370766ed..dba5a4c1 100644
--- a/simulators/gem5/src/cpu/simple/atomic.cc
+++ b/simulators/gem5/src/cpu/simple/atomic.cc
@@ -289,12 +289,20 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
             }
             dcache_access = true;
 
+			// FAIL*
+			#ifdef CONFIG_EVENT_TRAP
+			if(pkt.isError()) {
+				fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
+				fail::simulator.onTrap(cpu, 0);
+			}
+			#endif
+
             assert(!pkt.isError());
 
 			// FAIL*
 			#ifdef CONFIG_EVENT_MEMREAD
 			fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
-			fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), false, 0);
+			fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), false, instAddr());
 			#endif
 
             if (req->isLLSC()) {
@@ -396,12 +404,21 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
                         dcache_latency += dcachePort.sendAtomic(&pkt);
                 }
                 dcache_access = true;
+				
+				// FAIL*
+				#ifdef CONFIG_EVENT_TRAP
+				if(pkt.isError()) {
+					fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
+					fail::simulator.onTrap(cpu, 0);
+				}
+				#endif
+
                 assert(!pkt.isError());
 
 				// FAIL*
 				#ifdef CONFIG_EVENT_MEMWRITE
 				fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
-				fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), true, 0);
+				fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), true, instAddr());
 				#endif
 
                 if (req->isSwap()) {
@@ -496,11 +513,21 @@ AtomicSimpleCPU::tick()
                     else
                         icache_latency = icachePort.sendAtomic(&ifetch_pkt);
 
-                    assert(!ifetch_pkt.isError());
+					// FAIL*
+					#ifdef CONFIG_EVENT_TRAP
+                    if(ifetch_pkt.isError())
+					{
+						fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
+						fail::simulator.onTrap(cpu, 0);
+					}
+					#endif
+					
+					assert(!ifetch_pkt.isError());
+
 					// FAIL*
 					#ifdef CONFIG_EVENT_MEMREAD
 					fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
-					fail::simulator.onMemoryAccess(cpu, ifetch_pkt.getAddr(), ifetch_pkt.getSize(), false, 0);
+					fail::simulator.onMemoryAccess(cpu, ifetch_pkt.getAddr(), ifetch_pkt.getSize(), false, instAddr());
 					#endif
 
                     // ifetch_req is initialized to read the instruction directly
diff --git a/simulators/gem5/src/dev/arm/pl011.cc b/simulators/gem5/src/dev/arm/pl011.cc
index 4be7a5d9..34565083 100644
--- a/simulators/gem5/src/dev/arm/pl011.cc
+++ b/simulators/gem5/src/dev/arm/pl011.cc
@@ -51,6 +51,10 @@
 #include "mem/packet_access.hh"
 #include "sim/sim_exit.hh"
 
+#include "config/FailConfig.hpp"
+#include "sal/SALInst.hpp"
+
+
 Pl011::Pl011(const Params *p)
     : Uart(p), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), imsc(0),
       rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic),
@@ -180,8 +184,14 @@ Pl011::write(PacketPtr pkt)
 
     switch (daddr) {
         case UART_DR:
-          if ((data & 0xFF) == 0x04 && endOnEOT)
+          if ((data & 0xFF) == 0x04 && endOnEOT) {
+			// FAIL*
+			#ifdef CONFIG_EVENT_TRAP
+				fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0);
+				fail::simulator.onTrap(cpu, 0);
+			#endif
             exitSimLoop("UART received EOT", 0);
+		  }
 
         term->out(data & 0xFF);
 
diff --git a/simulators/gem5/src/dev/isa_fake.cc b/simulators/gem5/src/dev/isa_fake.cc
index 98d3f9d4..523fc8e8 100644
--- a/simulators/gem5/src/dev/isa_fake.cc
+++ b/simulators/gem5/src/dev/isa_fake.cc
@@ -39,6 +39,9 @@
 #include "mem/packet_access.hh"
 #include "sim/system.hh"
 
+#include "config/FailConfig.hpp"
+#include "sal/SALInst.hpp"
+
 using namespace std;
 
 IsaFake::IsaFake(Params *p)
@@ -113,7 +116,14 @@ IsaFake::write(PacketPtr pkt)
             data = pkt->get<uint8_t>();
             break;
           default:
-            panic("invalid access size!\n");
+			// FAIL*
+			#ifdef CONFIG_EVENT_TRAP
+			fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0);
+			fail::simulator.onTrap(cpu, 0);
+			#endif			
+			panic("invalid access size!\n");
+			
+            
         }
         warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
                 name(), pkt->getAddr(), pkt->getSize(), data);
diff --git a/simulators/gem5/src/mem/abstract_mem.cc b/simulators/gem5/src/mem/abstract_mem.cc
index dba5ecee..c84d6a50 100644
--- a/simulators/gem5/src/mem/abstract_mem.cc
+++ b/simulators/gem5/src/mem/abstract_mem.cc
@@ -62,9 +62,6 @@
 #include "mem/packet_access.hh"
 #include "sim/system.hh"
 
-#include "config/FailConfig.hpp"
-#include "sal/SALInst.hpp"
-
 using namespace std;
 
 AbstractMemory::AbstractMemory(const Params *p) :
diff --git a/simulators/gem5/src/mem/bus.cc b/simulators/gem5/src/mem/bus.cc
index 8040118d..032e9a43 100644
--- a/simulators/gem5/src/mem/bus.cc
+++ b/simulators/gem5/src/mem/bus.cc
@@ -53,6 +53,9 @@
 #include "debug/BusAddrRanges.hh"
 #include "mem/bus.hh"
 
+#include "config/FailConfig.hpp"
+#include "sal/SALInst.hpp"
+
 BaseBus::BaseBus(const BaseBusParams *p)
     : MemObject(p), clock(p->clock),
       headerCycles(p->header_cycles), width(p->width), tickNextIdle(0),
@@ -291,6 +294,11 @@ BaseBus::findPort(Addr addr)
 
     // we should use the range for the default port and it did not
     // match, or the default port is not set
+	// FAIL*
+	#ifdef CONFIG_EVENT_TRAP
+	fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0);
+	fail::simulator.onTrap(cpu, 0);
+	#endif
     fatal("Unable to find destination for addr %#llx on bus %s\n", addr,
           name());
 }