- Added signaling of trap situations needed in the weather-monitor to gem5.

- Fixed setting of instruction address for simulator.onMemoryAccess() calls.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2025 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/gem5/src/dev/arm/pl011.cc

@@ -51,6 +51,10 @@
 #include "mem/packet_access.hh"
 #include "sim/sim_exit.hh"
 
+#include "config/FailConfig.hpp"
+#include "sal/SALInst.hpp"
+
+
 Pl011::Pl011(const Params *p)
     : Uart(p), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), imsc(0),
       rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic),
@@ -180,8 +184,14 @@ Pl011::write(PacketPtr pkt)
 
     switch (daddr) {
         case UART_DR:
-          if ((data & 0xFF) == 0x04 && endOnEOT)
+          if ((data & 0xFF) == 0x04 && endOnEOT) {
+			// FAIL*
+			#ifdef CONFIG_EVENT_TRAP
+				fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0);
+				fail::simulator.onTrap(cpu, 0);
+			#endif
             exitSimLoop("UART received EOT", 0);
+		  }
 
         term->out(data & 0xFF);
 

simulators/gem5/src/dev/isa_fake.cc

@@ -39,6 +39,9 @@
 #include "mem/packet_access.hh"
 #include "sim/system.hh"
 
+#include "config/FailConfig.hpp"
+#include "sal/SALInst.hpp"
+
 using namespace std;
 
 IsaFake::IsaFake(Params *p)
@@ -113,7 +116,14 @@ IsaFake::write(PacketPtr pkt)
             data = pkt->get<uint8_t>();
             break;
           default:
-            panic("invalid access size!\n");
+			// FAIL*
+			#ifdef CONFIG_EVENT_TRAP
+			fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0);
+			fail::simulator.onTrap(cpu, 0);
+			#endif			
+			panic("invalid access size!\n");
+			
+            
         }
         warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
                 name(), pkt->getAddr(), pkt->getSize(), data);