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- Added signaling of trap situations needed in the weather-monitor to gem5.

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- Fixed setting of instruction address for simulator.onMemoryAccess() calls.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2025 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2013-01-30 23:59:24 +00:00
parent 640f5436cc
commit 9c62e4a7f2
5 changed files with 61 additions and 9 deletions
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35
simulators/gem5/src/cpu/simple/atomic.cc
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@ -289,12 +289,20 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
}
dcache_access = true;
// FAIL*
#ifdef CONFIG_EVENT_TRAP
if(pkt.isError()) {
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onTrap(cpu, 0);
}
#endif
assert(!pkt.isError());
// FAIL*
#ifdef CONFIG_EVENT_MEMREAD
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), false, 0);
fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), false, instAddr());
#endif
if (req->isLLSC()) {
@ -396,12 +404,21 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
dcache_latency += dcachePort.sendAtomic(&pkt);
}
dcache_access = true;
// FAIL*
#ifdef CONFIG_EVENT_TRAP
if(pkt.isError()) {
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onTrap(cpu, 0);
}
#endif
assert(!pkt.isError());
// FAIL*
#ifdef CONFIG_EVENT_MEMWRITE
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), true, 0);
fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), true, instAddr());
#endif
if (req->isSwap()) {
@ -496,11 +513,21 @@ AtomicSimpleCPU::tick()
else
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
assert(!ifetch_pkt.isError());
// FAIL*
#ifdef CONFIG_EVENT_TRAP
if(ifetch_pkt.isError())
{
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onTrap(cpu, 0);
}
#endif
assert(!ifetch_pkt.isError());
// FAIL*
#ifdef CONFIG_EVENT_MEMREAD
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onMemoryAccess(cpu, ifetch_pkt.getAddr(), ifetch_pkt.getSize(), false, 0);
fail::simulator.onMemoryAccess(cpu, ifetch_pkt.getAddr(), ifetch_pkt.getSize(), false, instAddr());
#endif
// ifetch_req is initialized to read the instruction directly