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core/sal: refactoring BochsCPU::get/setRegisterContent

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Removing the pData indirection that doesn't really simplify anything.

Change-Id: I98c15ffcd76faeac117bea4e1680dcb2dbdbc15f
This commit is contained in:
Horst Schirmeier
2018-12-07 15:34:26 +01:00
parent 171fe54330
commit 9625587fc4
1 changed files with 15 additions and 17 deletions
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32
src/core/sal/bochs/BochsCPU.cc
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@ -59,7 +59,6 @@ void BochsCPU::setRegisterContent(const Register* reg, regdata_t value)
{ {
assert(reg != NULL && "FATAL ERROR: reg-ptr cannot be NULL!"); assert(reg != NULL && "FATAL ERROR: reg-ptr cannot be NULL!");
regdata_t* pData;
switch (reg->getId()) { switch (reg->getId()) {
case RID_FLAGS: // EFLAGS/RFLAGS case RID_FLAGS: // EFLAGS/RFLAGS
#ifdef SIM_SUPPORT_64 #ifdef SIM_SUPPORT_64
@ -73,66 +72,65 @@ void BochsCPU::setRegisterContent(const Register* reg, regdata_t value)
BX_CPU(m_Id)->writeEFlags(value, 0xffffffff); BX_CPU(m_Id)->writeEFlags(value, 0xffffffff);
#endif #endif
BX_CPU(m_Id)->force_flags(); BX_CPU(m_Id)->force_flags();
return; break;
#ifndef __puma #ifndef __puma
case RID_CR0: case RID_CR0:
// untested // untested
BX_CPU(m_Id)->SetCR0(value); BX_CPU(m_Id)->SetCR0(value);
return; break;
case RID_CR2: case RID_CR2:
// untested // untested
BX_CPU(m_Id)->cr2 = value; BX_CPU(m_Id)->cr2 = value;
return; break;
case RID_CR3: case RID_CR3:
BX_CPU(m_Id)->SetCR3(value); BX_CPU(m_Id)->SetCR3(value);
return; break;
case RID_CR4: case RID_CR4:
// untested // untested
BX_CPU(m_Id)->SetCR4(value); BX_CPU(m_Id)->SetCR4(value);
return; break;
case RID_CS: case RID_CS:
// untested // untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_CS], value); BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_CS], value);
return; break;
case RID_DS: case RID_DS:
// untested // untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_DS], value); BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_DS], value);
return; break;
case RID_ES: case RID_ES:
// untested // untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_ES], value); BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_ES], value);
return; break;
case RID_FS: case RID_FS:
// untested // untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_FS], value); BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_FS], value);
return; break;
case RID_GS: case RID_GS:
// untested // untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_GS], value); BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_GS], value);
return; break;
case RID_SS: case RID_SS:
// untested // untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_SS], value); BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_SS], value);
return; break;
#endif #endif
#ifdef SIM_SUPPORT_64 #ifdef SIM_SUPPORT_64
case RID_PC: // program counter case RID_PC: // program counter
pData = &(BX_CPU(m_Id)->gen_reg[BX_64BIT_REG_RIP].rrx); BX_CPU(m_Id)->gen_reg[BX_64BIT_REG_RIP].rrx = value;
break; break;
default: // 64 bit general purpose registers default: // 64 bit general purpose registers
pData = &(BX_CPU(m_Id)->gen_reg[reg->getId()].rrx); BX_CPU(m_Id)->gen_reg[reg->getId()].rrx = value;
break; break;
#else // 32 bit mode #else // 32 bit mode
case RID_PC: // program counter case RID_PC: // program counter
pData = &(BX_CPU(m_Id)->gen_reg[BX_32BIT_REG_EIP].dword.erx); BX_CPU(m_Id)->gen_reg[BX_32BIT_REG_EIP].dword.erx = value;
break; break;
default: // 32 bit general purpose registers default: // 32 bit general purpose registers
pData = &(BX_CPU(m_Id)->gen_reg[reg->getId()].dword.erx); BX_CPU(m_Id)->gen_reg[reg->getId()].dword.erx = value;
break; break;
#endif // SIM_SUPPORT_64 #endif // SIM_SUPPORT_64
} }
*pData = value;
} }
} // end-of-namespace: fail } // end-of-namespace: fail