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core/sal: refactoring BochsCPU::get/setRegisterContent

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Using switch/case instead of an if cascade is more readable and has a
better chance to be optimized.

Change-Id: I41dc2cbdf8c14bd35c91520d74b476d7b522a3a4
This commit is contained in:
Horst Schirmeier
2018-11-20 18:43:27 +01:00
parent 60329bface
commit 171fe54330
1 changed files with 59 additions and 94 deletions
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153
src/core/sal/bochs/BochsCPU.cc
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@ -8,165 +8,130 @@ namespace fail {
regdata_t BochsCPU::getRegisterContent(const Register* reg) const
{
assert(reg != NULL && "FATAL ERROR: reg-ptr cannot be NULL!");
// TODO: BX_CPU(0) *always* correct?
if (reg->getId() == RID_FLAGS) { // EFLAGS register?
switch (reg->getId()) {
case RID_FLAGS: // EFLAGS/RFLAGS
return static_cast<regdata_t>(BX_CPU(m_Id)->read_eflags());
}
// untested
if (reg->getId() == RID_CR0) { // CR0 register?
case RID_CR0:
// untested
return static_cast<regdata_t>(BX_CPU(m_Id)->read_CR0());
}
// untested
if (reg->getId() == RID_CR2) { // CR2 register?
case RID_CR2:
// untested
return static_cast<regdata_t>(BX_CPU(m_Id)->cr2);
}
if (reg->getId() == RID_CR3) { // CR3 register?
case RID_CR3:
return static_cast<regdata_t>(BX_CPU(m_Id)->cr3);
}
// untested
if (reg->getId() == RID_CR4) { // CR4 register?
case RID_CR4:
// untested
return static_cast<regdata_t>(BX_CPU(m_Id)->read_CR4());
}
// untested
if (reg->getId() == RID_CS) { // CS register?
case RID_CS:
// untested
return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_CS].selector.value);
}
// untested
if (reg->getId() == RID_DS) { // DS register?
case RID_DS:
// untested
return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_DS].selector.value);
}
// untested
if (reg->getId() == RID_ES) { // ES register?
case RID_ES:
// untested
return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_ES].selector.value);
}
// untested
if (reg->getId() == RID_FS) { // FS register?
case RID_FS:
// untested
return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_FS].selector.value);
}
// untested
if (reg->getId() == RID_GS) { // GS register?
case RID_GS:
// untested
return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_GS].selector.value);
}
// untested
if (reg->getId() == RID_SS) { // SS register?
case RID_SS:
// untested
return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_SS].selector.value);
}
#ifdef SIM_SUPPORT_64
if (reg->getId() == RID_PC) // program counter?
case RID_PC: // program counter
return static_cast<regdata_t>(BX_CPU(m_Id)->gen_reg[BX_64BIT_REG_RIP].rrx);
else // 64 bit general purpose registers
default: // 64 bit general purpose registers
return static_cast<regdata_t>(BX_CPU(m_Id)->gen_reg[reg->getId()].rrx);
#else // 32 bit mode
if (reg->getId() == RID_PC)
case RID_PC: // program counter
return static_cast<regdata_t>(BX_CPU(m_Id)->gen_reg[BX_32BIT_REG_EIP].dword.erx);
else // 32 bit general purpose registers
default: // 32 bit general purpose registers
return static_cast<regdata_t>(BX_CPU(m_Id)->gen_reg[reg->getId()].dword.erx);
#endif // SIM_SUPPORT_64
}
}
void BochsCPU::setRegisterContent(const Register* reg, regdata_t value)
{
assert(reg != NULL && "FATAL ERROR: reg-ptr cannot be NULL!");
// TODO: BX_CPU(0) *always* correct?
if (reg->getId() == RID_FLAGS) { // EFLAGS register?
regdata_t* pData;
switch (reg->getId()) {
case RID_FLAGS: // EFLAGS/RFLAGS
#ifdef SIM_SUPPORT_64
{
// We are in 64 bit mode: Just assign the lower 32 bits!
regdata_t regdata = getRegisterContent(reg);
BX_CPU(m_Id)->writeEFlags((regdata & 0xFFFFFFFF00000000ULL) | (value & 0xFFFFFFFFULL),
0xffffffff);
}
#else
BX_CPU(m_Id)->writeEFlags(value, 0xffffffff);
#endif
BX_CPU(m_Id)->force_flags();
return;
}
#ifndef __puma
// untested
if (reg->getId() == RID_CR0) { // CR0 register?
case RID_CR0:
// untested
BX_CPU(m_Id)->SetCR0(value);
return;
}
// untested
if (reg->getId() == RID_CR2) { // CR2 register?
case RID_CR2:
// untested
BX_CPU(m_Id)->cr2 = value;
return;
}
if (reg->getId() == RID_CR3) { // CR3 register?
case RID_CR3:
BX_CPU(m_Id)->SetCR3(value);
return;
}
// untested
if (reg->getId() == RID_CR4) { // CR4 register?
case RID_CR4:
// untested
BX_CPU(m_Id)->SetCR4(value);
return;
}
// untested
if (reg->getId() == RID_CS) { // CS register?
case RID_CS:
// untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_CS], value);
return;
}
// untested
if (reg->getId() == RID_DS) { // DS register?
case RID_DS:
// untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_DS], value);
return;
}
// untested
if (reg->getId() == RID_ES) { // ES register?
case RID_ES:
// untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_ES], value);
return;
}
// untested
if (reg->getId() == RID_FS) { // FS register?
case RID_FS:
// untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_FS], value);
return;
}
// untested
if (reg->getId() == RID_GS) { // GS register?
case RID_GS:
// untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_GS], value);
return;
}
// untested
if (reg->getId() == RID_SS) { // SS register?
case RID_SS:
// untested
BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_SS], value);
return;
}
#endif
regdata_t* pData;
#ifdef SIM_SUPPORT_64
if (reg->getId() == RID_PC) // program counter?
case RID_PC: // program counter
pData = &(BX_CPU(m_Id)->gen_reg[BX_64BIT_REG_RIP].rrx);
else // 64 bit general purpose registers
break;
default: // 64 bit general purpose registers
pData = &(BX_CPU(m_Id)->gen_reg[reg->getId()].rrx);
break;
#else // 32 bit mode
if (reg->getId() == RID_PC)
case RID_PC: // program counter
pData = &(BX_CPU(m_Id)->gen_reg[BX_32BIT_REG_EIP].dword.erx);
else // 32 bit general purpose registers
break;
default: // 32 bit general purpose registers
pData = &(BX_CPU(m_Id)->gen_reg[reg->getId()].dword.erx);
break;
#endif // SIM_SUPPORT_64
}
*pData = value;
}