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T32: Memory access.

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Still not tested on real T32.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2105 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
hoffmann
2013-02-16 22:05:02 +00:00
parent d86d18bced
commit 2e16b8873b
6 changed files with 23 additions and 10 deletions
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8
src/core/sal/t32/T32ArmCPU.cc
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@ -4,6 +4,8 @@
namespace fail { namespace fail {
static const uint64_t lower = 0x00000000ffffffff;
regdata_t T32ArmCPU::getRegisterContent(Register* reg) const regdata_t T32ArmCPU::getRegisterContent(Register* reg) const
{ {
// T32_ReadRegister wants a mask of bits representig the registers to read: // T32_ReadRegister wants a mask of bits representig the registers to read:
@ -11,11 +13,11 @@ regdata_t T32ArmCPU::getRegisterContent(Register* reg) const
// mask1 // mask1
// 0000 0000 0000 0000 0001 0010 -> R1/R4 // 0000 0000 0000 0000 0001 0010 -> R1/R4
// mask2 // mask2
// 1000 0000 0000 0000 0001 0010 -> R63 // 1000 0000 0000 0000 0000 0000 -> R63
uint64_t mask = (1 << reg->getIndex()); uint64_t mask = (1 << reg->getIndex());
if(mask){ if(mask){
if( T32_ReadRegister(static_cast<dword>(mask & 0xffffffff), static_cast<dword>(mask >> 32), m_regbuffer) == 0 ){ if( T32_ReadRegister(static_cast<dword>(mask & lower ), static_cast<dword>(mask >> 32), m_regbuffer) == 0 ){
// No error, return value. // No error, return value.
return m_regbuffer[reg->getIndex()]; return m_regbuffer[reg->getIndex()];
} else { } else {
@ -30,7 +32,7 @@ void T32ArmCPU::setRegisterContent(Register* reg, regdata_t value)
uint64_t mask = (1 << reg->getIndex()); uint64_t mask = (1 << reg->getIndex());
if(mask){ if(mask){
if( T32_WriteRegister(static_cast<dword>(mask & 0xffffffff), static_cast<dword>(mask >> 32), m_regbuffer) == 0 ){ if( T32_WriteRegister(static_cast<dword>(mask & lower), static_cast<dword>(mask >> 32), m_regbuffer) == 0 ){
// No error, return value. // No error, return value.
return; return;
} else { } else {

4
src/core/sal/t32/T32ArmCPU.hpp
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@ -18,9 +18,9 @@ namespace fail {
class T32ArmCPU : public ArmArchitecture, public ArmCPUState { class T32ArmCPU : public ArmArchitecture, public ArmCPUState {
public: public:
/** /**
* Creates a new gem5 CPU for ARM based targets. * Creates a new T32 CPU for ARM based targets.
* @param id the unique ID of the CPU to be created (the first CPU0 has ID 0) * @param id the unique ID of the CPU to be created (the first CPU0 has ID 0)
* @param system the gem5 system object * @param system the T32 system object
*/ */
T32ArmCPU(unsigned int id = 0) : m_Id(id) { } T32ArmCPU(unsigned int id = 0) : m_Id(id) { }
virtual ~T32ArmCPU() { } virtual ~T32ArmCPU() { }

2
src/core/sal/t32/T32Controller.hpp
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@ -13,9 +13,9 @@ namespace fail {
class T32Controller : public SimulatorController { class T32Controller : public SimulatorController {
public: public:
void startup(); void startup();
T32Controller() : SimulatorController(new T32MemoryManager()) { };
~T32Controller(); ~T32Controller();
/* ******************************************************************** /* ********************************************************************
* Simulator Controller & Access API: * Simulator Controller & Access API:
* ********************************************************************/ * ********************************************************************/

5
src/core/sal/t32/T32Listener.ah
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@ -9,16 +9,15 @@
#include "../SALInst.hpp" #include "../SALInst.hpp"
aspect T32Listener aspect T32Listener
{
advice "fail::BPSingleListener" : slice class advice "fail::BPSingleListener" : slice class
{ {
public: public:
bool onAddition() bool onAddition()
{ {
// Setup Breakpoint in T32 // Setup Breakpoint in T32
std::cout << "T32Listener::onAddition" << std::endl; std::cout << "T32Listener::onAddition" << std::endl;
// Enable Breakpoint
return true; return true;
} }

2
src/core/sal/t32/T32Memory.hpp
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@ -2,7 +2,7 @@
#define __T32_MEMORY_HPP__ #define __T32_MEMORY_HPP__
#include "../Memory.hpp" #include "../Memory.hpp"
#include <iostream>
#include <t32.h> #include <t32.h>
namespace fail { namespace fail {

12
src/experiments/vezs-example/experiment.cc
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@ -32,6 +32,18 @@ bool VEZSExperiment::run()
m_log << "Register R1: 0x" << hex << simulator.getCPU(0).getRegisterContent(reg) << endl; m_log << "Register R1: 0x" << hex << simulator.getCPU(0).getRegisterContent(reg) << endl;
simulator.getCPU(0).setRegisterContent(reg, 0x23); simulator.getCPU(0).setRegisterContent(reg, 0x23);
address_t targetaddress = 0x12345678;
MemoryManager& mm = simulator.getMemoryManager();
mm.setByte(targetaddress, 0x42);
mm.getByte(targetaddress);
uint8_t tb[] = {0xaa, 0xbb, 0xcc, 0xdd};
mm.setBytes(targetaddress, 4, tb);
*((uint32_t*)(tb)) = 0; // clear array.
// read back bytes
mm.getBytes(targetaddress, 4, tb);
// Explicitly terminate, or the simulator will continue to run. // Explicitly terminate, or the simulator will continue to run.
simulator.terminate(); simulator.terminate();
} }