diff --git a/src/core/sal/t32/T32ArmCPU.cc b/src/core/sal/t32/T32ArmCPU.cc
index 20b40003..d6704deb 100644
--- a/src/core/sal/t32/T32ArmCPU.cc
+++ b/src/core/sal/t32/T32ArmCPU.cc
@@ -4,6 +4,8 @@
 
 namespace fail {
 
+static const uint64_t lower = 0x00000000ffffffff;
+
 regdata_t T32ArmCPU::getRegisterContent(Register* reg) const
 {
   // T32_ReadRegister wants a mask of bits representig the registers to read:
@@ -11,11 +13,11 @@ regdata_t T32ArmCPU::getRegisterContent(Register* reg) const
   //             mask1
   // 0000 0000 0000 0000 0001 0010 ->  R1/R4
   //             mask2
-  // 1000 0000 0000 0000 0001 0010 ->  R63
+  // 1000 0000 0000 0000 0000 0000 ->  R63
   uint64_t mask = (1 << reg->getIndex());
 
   if(mask){
-    if( T32_ReadRegister(static_cast<dword>(mask & 0xffffffff), static_cast<dword>(mask >> 32), m_regbuffer) == 0 ){
+    if( T32_ReadRegister(static_cast<dword>(mask & lower ), static_cast<dword>(mask >> 32), m_regbuffer) == 0 ){
     // No error, return value.
       return m_regbuffer[reg->getIndex()];
     } else {
@@ -30,7 +32,7 @@ void T32ArmCPU::setRegisterContent(Register* reg, regdata_t value)
   uint64_t mask = (1 << reg->getIndex());
 
   if(mask){
-    if( T32_WriteRegister(static_cast<dword>(mask & 0xffffffff), static_cast<dword>(mask >> 32), m_regbuffer) == 0 ){
+    if( T32_WriteRegister(static_cast<dword>(mask & lower), static_cast<dword>(mask >> 32), m_regbuffer) == 0 ){
       // No error, return value.
       return;
     } else {
diff --git a/src/core/sal/t32/T32ArmCPU.hpp b/src/core/sal/t32/T32ArmCPU.hpp
index a4464e88..9210f715 100644
--- a/src/core/sal/t32/T32ArmCPU.hpp
+++ b/src/core/sal/t32/T32ArmCPU.hpp
@@ -18,9 +18,9 @@ namespace fail {
 class T32ArmCPU : public ArmArchitecture, public ArmCPUState {
 public:
 	/**
-	 * Creates a new gem5 CPU for ARM based targets.
+	 * Creates a new T32 CPU for ARM based targets.
 	 * @param id the unique ID of the CPU to be created (the first CPU0 has ID 0)
-	 * @param system the gem5 system object
+	 * @param system the T32 system object
 	 */
 	T32ArmCPU(unsigned int id = 0) : m_Id(id) { }
 	virtual ~T32ArmCPU() { }
diff --git a/src/core/sal/t32/T32Controller.hpp b/src/core/sal/t32/T32Controller.hpp
index 7ed6da9c..b8b52c10 100644
--- a/src/core/sal/t32/T32Controller.hpp
+++ b/src/core/sal/t32/T32Controller.hpp
@@ -13,9 +13,9 @@ namespace fail {
 class T32Controller : public SimulatorController {
 public:
   void startup();
+  T32Controller() : SimulatorController(new T32MemoryManager()) { };
 	~T32Controller();
 
-
 	/* ********************************************************************
 	 * Simulator Controller & Access API:
 	 * ********************************************************************/
diff --git a/src/core/sal/t32/T32Listener.ah b/src/core/sal/t32/T32Listener.ah
index b27cbc02..b4eded29 100644
--- a/src/core/sal/t32/T32Listener.ah
+++ b/src/core/sal/t32/T32Listener.ah
@@ -9,16 +9,15 @@
 #include "../SALInst.hpp"
 
 aspect T32Listener
-
+{
 	advice "fail::BPSingleListener" : slice class
 	{
 	public:
 		bool onAddition()
 		{
-
       // Setup Breakpoint in T32
 			std::cout << "T32Listener::onAddition" << std::endl;
-
+      // Enable Breakpoint
 
 			return true;
 		}
diff --git a/src/core/sal/t32/T32Memory.hpp b/src/core/sal/t32/T32Memory.hpp
index 7b397605..aa32cdeb 100644
--- a/src/core/sal/t32/T32Memory.hpp
+++ b/src/core/sal/t32/T32Memory.hpp
@@ -2,7 +2,7 @@
   #define __T32_MEMORY_HPP__
 
 #include "../Memory.hpp"
-
+#include <iostream>
 #include <t32.h>
 
 namespace fail {
diff --git a/src/experiments/vezs-example/experiment.cc b/src/experiments/vezs-example/experiment.cc
index f2ccb037..3e7d123b 100644
--- a/src/experiments/vezs-example/experiment.cc
+++ b/src/experiments/vezs-example/experiment.cc
@@ -32,6 +32,18 @@ bool VEZSExperiment::run()
   m_log << "Register R1: 0x" << hex << simulator.getCPU(0).getRegisterContent(reg) << endl;
 
   simulator.getCPU(0).setRegisterContent(reg, 0x23);
+
+  address_t targetaddress = 0x12345678;
+  MemoryManager& mm = simulator.getMemoryManager();
+  mm.setByte(targetaddress, 0x42);
+  mm.getByte(targetaddress);
+
+  uint8_t tb[] = {0xaa, 0xbb, 0xcc, 0xdd};
+  mm.setBytes(targetaddress, 4, tb);
+  *((uint32_t*)(tb)) = 0; // clear array.
+  // read back bytes
+  mm.getBytes(targetaddress, 4, tb);
+
   // Explicitly terminate, or the simulator will continue to run.
   simulator.terminate();
 }