Commit Graph

20 Commits

Author SHA1 Message Date
fe5e7a9981 Implement Memory64 support for AOT (#3362)
Refer to:
https://github.com/bytecodealliance/wasm-micro-runtime/pull/3266
https://github.com/bytecodealliance/wasm-micro-runtime/issues/3091
2024-05-13 11:03:38 +08:00
1c2a8fca4e Fix some more spelling issues (#3393) 2024-05-08 09:30:29 +08:00
ca61184ced Fix some spelling issues (#3385)
Fix some of the spelling issues found by CSpell.
2024-05-06 07:56:48 +08:00
bcc2a2d2e1 Sync simd opcode definitions spec (#3290)
Remove undefined simd opcodes.
2024-04-09 16:54:42 +08:00
75a2b98eb4 simd-128: The input lanes of integer-to-integer narrowing ops should be interpreted as signed (#2850)
https://github.com/WebAssembly/spec/blob/main/proposals/simd/SIMD.md#integer-to-integer-narrowing
2024-01-03 09:51:58 +08:00
caf805ece7 Fix AOT compiler simd shift opcodes (#2715) 2023-11-03 10:38:53 +08:00
3c17a36ccb Patch implementations of vfbinop(min,max,pmin,pax) (#2584)
According to the specification,
- fNxM_pmin/max returns v1 or v2 based on flt(v1,v2) result
- fNxM_min/max returns +/-NaN, +/-Inf, v1 or v2 based on more than
  flt(v1,v2) result

Fixes issue #2561.
2023-09-28 09:32:01 +08:00
76be848ec3 Implement the segue optimization for LLVM AOT/JIT (#2230)
Segue is an optimization technology which uses x86 segment register to store
the WebAssembly linear memory base address, so as to remove most of the cost
of SFI (Software-based Fault Isolation) base addition and free up a general
purpose register, by this way it may:
- Improve the performance of JIT/AOT
- Reduce the footprint of JIT/AOT, the JIT/AOT code generated is smaller
- Reduce the compilation time of JIT/AOT

This PR uses the x86-64 GS segment register to apply the optimization, currently
it supports linux and linux-sgx platforms on x86-64 target. By default it is disabled,
developer can use the option below to enable it for wamrc and iwasm(with LLVM
JIT enabled):
```bash
wamrc --enable-segue=[<flags>] -o output_file wasm_file
iwasm --enable-segue=[<flags>] wasm_file [args...]
```
`flags` can be:
    i32.load, i64.load, f32.load, f64.load, v128.load,
    i32.store, i64.store, f32.store, f64.store, v128.store
Use comma to separate them, e.g. `--enable-segue=i32.load,i64.store`,
and `--enable-segue` means all flags are added.

Acknowledgement:
Many thanks to Intel Labs, UC San Diego and UT Austin teams for introducing this
technology and the great support and guidance!

Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
Co-authored-by: Vahldiek-oberwagner, Anjo Lucas <anjo.lucas.vahldiek-oberwagner@intel.com>
2023-05-26 10:13:33 +08:00
29dee732e9 Fix typo in simd_conversions.c (#1428)
Change "==" to "=" when setting trunc_type[] array elements.
2022-08-29 18:01:19 +08:00
5e238322c2 Enable aot compiler with llvm-14/15 (#1252)
Enable aot compiler and jit based on llvm-14.0 and llvm-15.0git,
replace LLVMBuildLoad/LLVMBuildInBoundsGEP/LLVMBuildCall with
LLVMBuildLoad2/LLVMBuildInBoundsGEP2/LLVMBuildCall2, and pass
them with related types, so as to meet the requirements of opaque
pointers.

And fix several compilation errors for llvm-14.0/15.0git.

Most spec cases and standalone cases are tested.
2022-06-28 14:53:01 +08:00
fb4afc7ca4 Apply clang-format for core/iwasm compilation and libraries (#784)
Apply clang-format for core/iwasm/compilation and core/iwasm/libraries files.
Add wasm-c-api empty_imports sample to workflow test.
And enable triggering workflow when core/config.h changes.
2021-10-13 15:13:00 +08:00
b5a67cb91e Fix several issues of document, spec test script and simd (#767)
Fix document issues: add ARC to supported targets, fix how to build wamrc for MacOS.
Fix spec case test script issue: the latest wabt has enabled simd by default, no need to
add "--enable-simd" option for test script.
Fix simd LLVM IR compilation issue: using index calculated by opcode to access array
element should not be out of array boundary, add bh_assert() for it.

Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
2021-09-29 11:13:38 +08:00
7be0d385a6 Implement SIMD latest opcodes and update LLVM to 13.0 (#758)
Implement the latest SIMD opcodes and update LLVM 13.0,
update the llvm build scripts, update the sample workloads‘ build scripts,
and build customized wasi-sdk to build some workloads.
Also refine the CI rules.

Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
2021-09-17 19:12:57 +08:00
db695fada4 Implement XIP feature and enable ARC target support (#694)
Implement XIP (Execution In Place) feature for AOT mode to enable running the AOT code inside AOT file directly, without memory mapping the executable memory for AOT code and applying relocations for text section. Developer can use wamrc with "--enable-indirect-mode --disable-llvm-intrinsics" flags to generate the AOT file and run iwasm with "--xip" flag. Known issues: there might still be some relocations in the text section which access the ".rodata" like sections.

And also enable ARC target support for both interpreter mode and AOT mode.

Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
2021-08-12 17:44:39 +08:00
7706e4b151 Re-org SIMD code structure for non-x86 target (#611) 2021-04-13 15:23:22 +08:00
46db353017 Enable SIMD for AARCH64 Platform (#11) (#610)
Signed-off-by: Wu Zhongmin <zhongmin.wzm@antgroup.com>
Signed-off-by: Xiaokang Qin <xiaokang.qxk@antgroup.com>

Co-authored-by: Wu Zhongmin <zhongmin.wzm@antgroup.com>

Co-authored-by: Wu Zhongmin <zhongmin.wzm@antgroup.com>
2021-04-13 14:45:51 +08:00
02d27e13ee Fix some compilation warnings and enable Windows JIT (#586) 2021-03-22 19:28:51 +08:00
a5188f5574 Add checks to avoid wasm_runtime_malloc memory with size 0 (#507)
In some platforms, allocating memory with size 0 may return NULL but not an empty memory block, which causes runtime load, instantiate or execute wasm/aot file failed. We add checks to try to avoid allocating memory in runtime if the size is 0. And in wasm_runtime_malloc/free, output warning if allocate memory with size 0 and free memory with NULL ptr.
Also fix some coding style issues, fix handle riscv32 ilp32d issue, and fix several wasm-c-api issues.

Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
2021-01-28 16:16:02 +08:00
ad35c3c21b Implement SIMD float ceil/floor/trunc/nearest opcodes (#472)
Implement SIMD f32x4/f64x2 ceil/floor/trunc/nearest opcodes

Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
2020-12-16 15:33:25 +08:00
a3074df21b Import SIMD feature and add some workload samples (#438) 2020-11-05 18:15:15 +08:00