Commit Graph

23 Commits

Author SHA1 Message Date
1c2a8fca4e Fix some more spelling issues (#3393) 2024-05-08 09:30:29 +08:00
9c8551cf75 Add cmake flag to control aot intrinsics (#3261)
Add cmake variable `-DWAMR_BUILD_AOT_INTRINSICS=1/0` to enable/disable
the aot intrinsic functions, which are normally used by AOT XIP feature, and
can be disabled to reduce the aot runtime binary size.

And refactor the code in aot_intrinsics.h/.c.
2024-04-01 11:26:05 +08:00
aafea39b8c Add "--enable-builtin-intrinsics=<flags>" option to wamrc (#2341)
Refer to doc/xip.md for details.
2023-07-06 18:20:35 +08:00
d309091706 Register missing symbols for f32 to 64 bit integer conversion (#1850) 2022-12-30 15:21:25 +08:00
d1fe589d43 Fix fmin/fmax in AOT XIP intrinsics (#1848) 2022-12-29 18:48:55 +08:00
41eb938a95 Fix equal check in AOT XIP float cmp intrinsic (#1847) 2022-12-29 18:11:05 +08:00
6c7ca90229 Use float version library routine for XIP aot_intrinsic_xxx APIs (#1846) 2022-12-29 16:49:27 +08:00
ef4e795dba Implement i32.div_s (#1792) 2022-12-13 10:48:51 +08:00
f6bef1e604 Implement i32.rem_s and i32.rem_u intrinsic (#1789) 2022-12-08 09:38:20 +08:00
4b0660cf24 Fix missing float cmp for XIP (#1699) 2022-11-14 11:58:38 +08:00
94cecbe4cb Fix XIP issues of fp to int cast and int rem/div (#1654) 2022-11-01 20:29:07 +08:00
e517dbc7b2 XIP adaptation for xtensa platform (#1636)
Add macro WASM_ENABLE_WORD_ALING_READ to enable reading
1/2/4 and n bytes data from vram buffer, which requires 4-byte addr
alignment reading.

Eliminate XIP AOT relocations related to the below ones:
   i32_div_u, f32_min, f32_max, f32_ceil, f32_floor, f32_trunc, f32_rint
2022-10-31 17:25:24 +08:00
73809efb5d Fix XIP issue caused by rem_s on RISC-V (#1619) 2022-10-19 16:46:26 +08:00
2178787664 Implement i64.div and i64.rem intrinsics (#1375) 2022-08-12 11:09:06 +08:00
6922f3ac68 Implement xtensa XIP (#1202)
Lookup table for i32.const and i64.const for xtensa XIP
Lookup const offset from table for load/store opcodes for xtensa XIP
Fill capability flags for xtensa XIP
Enable lower switch pass for xtensa XIP
2022-08-04 14:42:28 +08:00
a41c1ad85c Don't use constant float table on arm and riscv (#903)
Don't use constant float table on arm and riscv as LLVM doesn't generate
.LPCI/.rodata like relocations on them, the float/double constants are encoded
into instructions directly, so no need to lookup them from constant table.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-20 11:10:52 +08:00
208cafc776 Add new E_TYPE_XIP to indicate XIP mode (#874)
Emit e_type = E_TYPE_XIP in target info section to indicate that it is
an XIP file, and replace related checks in aot loader.
2021-12-08 18:43:08 +08:00
8d1c56bda4 Implement atomic and memset/memmove/memcpy intrinsic for riscv (#841)
- Lower aotmic instruction to non-atomic form on some platforms
- Lower memset/memmove/memcpy for XIP
- Disable rtti in cmake
2021-11-30 17:10:14 +08:00
52b6c73d9c Apply clang-format for more src files and update spec test script (#775)
Apply clang-format for core/iwasm/include, core/iwasm/common and
core/iwasm/aot files.

Update spec cases test script:
- Checkout latest commit of https://github.com/WebAssembly/spec
- Checkout main branch but not master of https://github.com/WebAssembly/threads
- Update wabt to latest version

And update source debugging document.

Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
2021-10-08 17:47:11 +08:00
b31804b64e Apply aot intrinsics to riscv
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Change-Id: If1e813f5f8ead2c0d9b640f8ea4e87e2155db534
2021-09-09 07:59:12 +00:00
cef7d35be1 Implement float and integer conversion intrinsics (#718) 2021-09-02 16:39:53 +08:00
6ef74778c7 Correct confusing usage of intirnsic check (#707) 2021-08-27 19:03:18 +08:00
db695fada4 Implement XIP feature and enable ARC target support (#694)
Implement XIP (Execution In Place) feature for AOT mode to enable running the AOT code inside AOT file directly, without memory mapping the executable memory for AOT code and applying relocations for text section. Developer can use wamrc with "--enable-indirect-mode --disable-llvm-intrinsics" flags to generate the AOT file and run iwasm with "--xip" flag. Known issues: there might still be some relocations in the text section which access the ".rodata" like sections.

And also enable ARC target support for both interpreter mode and AOT mode.

Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
2021-08-12 17:44:39 +08:00