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Bring up WAMR on esp32-s3 device (#2348)

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esp32-s3's instruction memory and data memory can be accessed through mutual mirroring way,
so we define a new feature named as WASM_MEM_DUAL_BUS_MIRROR.
This commit is contained in:
dongsheng28849455
2023-07-21 07:54:13 +08:00
committed by GitHub
parent 57abdfdb5c
commit fbe072c0d3
6 changed files with 122 additions and 3 deletions
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5
core/shared/platform/include/platform_api_vmcore.h
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@ -129,6 +129,11 @@ os_munmap(void *addr, size_t size);
int
os_mprotect(void *addr, size_t size, int prot);
#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
void *
os_get_dbus_mirror(void *ibus);
#endif
/**
* Flush cpu data cache, in some CPUs, after applying relocation to the
* AOT code, the code may haven't been written back to the cpu data cache,

81
core/shared/platform/nuttx/nuttx_platform.c
View File

@ -10,6 +10,46 @@
#include <nuttx/arch.h>
#endif
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
/*
* TODO: Move these methods below the operating system level
*/
#define MEM_DUAL_BUS_OFFSET (0x42000000 - 0x3C000000)
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
#define IRAM_ATTR locate_data(".iram1")
#define in_ibus_ext(addr) \
(((uint32)addr >= IRAM0_CACHE_ADDRESS_LOW) \
&& ((uint32)addr < IRAM0_CACHE_ADDRESS_HIGH))
void IRAM_ATTR
bus_sync(void)
{
extern void cache_writeback_all(void);
extern uint32_t Cache_Disable_ICache(void);
extern void Cache_Enable_ICache(uint32_t autoload);
irqstate_t flags;
uint32_t preload;
flags = enter_critical_section();
cache_writeback_all();
preload = Cache_Disable_ICache();
Cache_Enable_ICache(preload);
leave_critical_section(flags);
}
#else
#define MEM_DUAL_BUS_OFFSET (0)
#define IRAM0_CACHE_ADDRESS_LOW (0)
#define IRAM0_CACHE_ADDRESS_HIGH (0)
#define in_ibus_ext(addr) (0)
static void
bus_sync(void)
{}
#endif
int
bh_platform_init()
{
@ -47,6 +87,10 @@ os_dumps_proc_mem_info(char *out, unsigned int size)
void *
os_mmap(void *hint, size_t size, int prot, int flags)
{
#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
void *i_addr, *d_addr;
#endif
#if defined(CONFIG_ARCH_USE_TEXT_HEAP)
if ((prot & MMAP_PROT_EXEC) != 0) {
return up_textheap_memalign(sizeof(void *), size);
@ -55,6 +99,17 @@ os_mmap(void *hint, size_t size, int prot, int flags)
if ((uint64)size >= UINT32_MAX)
return NULL;
#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
if ((prot & MMAP_PROT_EXEC) != 0) {
d_addr = malloc((uint32)size);
if (d_addr == NULL) {
return NULL;
}
i_addr = (void *)((uint8 *)d_addr + MEM_DUAL_BUS_OFFSET);
return in_ibus_ext(i_addr) ? i_addr : d_addr;
}
#endif
return malloc((uint32)size);
}
@ -67,7 +122,14 @@ os_munmap(void *addr, size_t size)
return;
}
#endif
return free(addr);
#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
if (in_ibus_ext(addr)) {
free((void *)((uint8 *)addr - MEM_DUAL_BUS_OFFSET));
return;
}
#endif
free(addr);
}
int
@ -78,7 +140,22 @@ os_mprotect(void *addr, size_t size, int prot)
void
os_dcache_flush()
{}
{
bus_sync();
}
#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
void *
os_get_dbus_mirror(void *ibus)
{
if (in_ibus_ext(ibus)) {
return (void *)((uint8 *)ibus - MEM_DUAL_BUS_OFFSET);
}
else {
return ibus;
}
}
#endif
/* If AT_FDCWD is provided, maybe we have openat family */
#if !defined(AT_FDCWD)