Implement AOT support for RISCV (#649)

Enable RISCV AOT support, the supported ABIs are LP64 and LP64D for riscv64, ILP32 and ILP32D for riscv32.
For wamrc:
    use --target=riscv64/riscv32 to specify the target arch of output AOT file,
    use --target-abi=lp64d/lp64/ilp32d/ilp32 to specify the target ABI,
    if --target-abi isn't specified, by default lp64d is used for riscv64, and ilp32d is used for riscv32.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Co-authored-by: wenyongh <wenyong.huang@intel.com>

core/iwasm/compilation/aot_emit_aot_file.c

@@ -1752,6 +1752,7 @@ is_data_section(LLVMSectionIteratorRef sec_itr, char *section_name)
     uint32 relocation_count = 0;
 
     return (!strcmp(section_name, ".data")
+            || !strcmp(section_name, ".sdata")
             || !strcmp(section_name, ".rodata")
             /* ".rodata.cst4/8/16/.." */
             || !strncmp(section_name, ".rodata.cst", strlen(".rodata.cst"))
@@ -1970,10 +1971,13 @@ aot_resolve_object_relocation_group(AOTObjectData *obj_data,
         relocation->relocation_type = (uint32)type;
         relocation->symbol_name = (char *)LLVMGetSymbolName(rel_sym);
 
-        /* for ".LCPIxxx" relocation, transform the symbol name to real
-         * section name and set addend to the symbol address */
+        /* for ".LCPIxxx", ".LJTIxxx" and ".LBBxxx" relocation,
+         * transform the symbol name to real section name and set
+         * addend to the offset of the symbol in the real section */
         if (relocation->symbol_name
-            && str_starts_with(relocation->symbol_name, ".LCPI")) {
+            && (str_starts_with(relocation->symbol_name, ".LCPI")
+                || str_starts_with(relocation->symbol_name, ".LJTI")
+                || str_starts_with(relocation->symbol_name, ".LBB"))) {
             /* change relocation->relocation_addend and relocation->symbol_name */
             LLVMSectionIteratorRef contain_section;
             if (!(contain_section
@@ -2012,6 +2016,8 @@ is_relocation_section_name(char *section_name)
             || !strcmp(section_name, ".rela.literal")
             || !strcmp(section_name, ".rela.data")
             || !strcmp(section_name, ".rel.data")
+            || !strcmp(section_name, ".rela.sdata")
+            || !strcmp(section_name, ".rel.sdata")
             || !strcmp(section_name, ".rela.rodata")
             || !strcmp(section_name, ".rel.rodata")
             /* ".rela.rodata.cst4/8/16/.." */

core/iwasm/compilation/aot_emit_numberic.c

@@ -767,6 +767,12 @@ is_target_mips(AOTCompContext *comp_ctx)
     return !strncmp(comp_ctx->target_arch, "mips", 4);
 }
 
+static bool
+is_target_riscv(AOTCompContext *comp_ctx)
+{
+    return !strncmp(comp_ctx->target_arch, "riscv", 5);
+}
+
 static bool
 is_targeting_soft_float(AOTCompContext *comp_ctx, bool is_f32)
 {
@@ -796,6 +802,8 @@ is_targeting_soft_float(AOTCompContext *comp_ctx, bool is_f32)
          * so user must specify '--cpu-features=-fp' to wamrc if the target
          * doesn't have or enable Floating-Point Coprocessor Option on xtensa. */
         ret = (!is_f32 || strstr(feature_string, "-fp")) ? true : false;
+    else if (is_target_riscv(comp_ctx))
+        ret = !strstr(feature_string, "+d") ? true : false;
     else
         ret = true;
 

core/iwasm/compilation/aot_llvm.c

@@ -1087,14 +1087,22 @@ static ArchItem valid_archs[] = {
     { "thumbv8r", true },
     { "thumbv8m.base", true },
     { "thumbv8m.main", true },
-    { "thumbv8.1m.main", true }
+    { "thumbv8.1m.main", true },
+    { "riscv32", true},
+    { "riscv64", true}
 };
 
 static const char *valid_abis[] = {
     "gnu",
     "eabi",
     "gnueabihf",
-    "msvc"
+    "msvc",
+    "ilp32",
+    "ilp32f",
+    "ilp32d",
+    "lp64",
+    "lp64f",
+    "lp64d"
 };
 
 static void
@@ -1184,7 +1192,7 @@ aot_create_comp_context(AOTCompData *comp_data,
     char *cpu = NULL, *features, buf[128];
     char *triple_norm_new = NULL, *cpu_new = NULL;
     char *err = NULL, *fp_round= "round.tonearest", *fp_exce = "fpexcept.strict";
-    char triple_buf[32] = {0};
+    char triple_buf[32] = { 0 }, features_buf[128] = { 0 };
     uint32 opt_level, size_level;
     LLVMCodeModel code_model;
     LLVMTargetDataRef target_data_ref;
@@ -1323,6 +1331,14 @@ aot_create_comp_context(AOTCompData *comp_data,
             goto fail;
         }
 
+        /* Set default abi for riscv target */
+        if (arch && !strncmp(arch, "riscv", 5) && !abi) {
+            if (!strcmp(arch, "riscv64"))
+                abi = "lp64d";
+            else
+                abi = "ilp32d";
+        }
+
         if (arch) {
             /* Construct target triple: <arch>-<vendor>-<sys>-<abi> */
             const char *vendor_sys;
@@ -1394,6 +1410,29 @@ aot_create_comp_context(AOTCompData *comp_data,
             goto fail;
         }
 
+        /* Add module flag and cpu feature for riscv target */
+        if (arch && !strncmp(arch, "riscv", 5)) {
+            LLVMMetadataRef meta_target_abi;
+
+            if (!(meta_target_abi = LLVMMDStringInContext2(comp_ctx->context,
+                                                           abi, strlen(abi)))) {
+                aot_set_last_error("create metadata string failed.");
+                goto fail;
+            }
+            LLVMAddModuleFlag(comp_ctx->module, LLVMModuleFlagBehaviorError,
+                          "target-abi", strlen("target-abi"), meta_target_abi);
+
+            if (!strcmp(abi, "lp64d") || !strcmp(abi, "ilp32d")) {
+                if (features) {
+                    snprintf(features_buf, sizeof(features_buf),
+                             "%s%s", features, ",+d");
+                    features = features_buf;
+                }
+                else
+                    features = "+d";
+            }
+        }
+
         if (!features)
             features = "";