Implement XIP feature and enable ARC target support (#694)
Implement XIP (Execution In Place) feature for AOT mode to enable running the AOT code inside AOT file directly, without memory mapping the executable memory for AOT code and applying relocations for text section. Developer can use wamrc with "--enable-indirect-mode --disable-llvm-intrinsics" flags to generate the AOT file and run iwasm with "--xip" flag. Known issues: there might still be some relocations in the text section which access the ".rodata" like sections. And also enable ARC target support for both interpreter mode and AOT mode. Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
This commit is contained in:
Wenyong Huang
237
core/iwasm/aot/arch/aot_reloc_arc.c
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237
core/iwasm/aot/arch/aot_reloc_arc.c
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/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*/
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#include "aot_reloc.h"
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#define R_ARC_S21H_PCREL 14
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#define R_ARC_S21W_PCREL 15
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#define R_ARC_S25H_PCREL 16
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#define R_ARC_S25W_PCREL 17
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#define R_ARC_32 4
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#define R_ARC_32_ME 27
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void __st_r13_to_r15();
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void __st_r13_to_r16();
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void __st_r13_to_r17();
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void __st_r13_to_r18();
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void __st_r13_to_r19();
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void __st_r13_to_r20();
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void __st_r13_to_r21();
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void __st_r13_to_r22();
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void __st_r13_to_r23();
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void __st_r13_to_r24();
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void __st_r13_to_r25();
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void __ld_r13_to_r15();
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void __ld_r13_to_r16();
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void __ld_r13_to_r17();
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void __ld_r13_to_r18();
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void __ld_r13_to_r19();
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void __ld_r13_to_r20();
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void __ld_r13_to_r21();
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void __ld_r13_to_r22();
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void __ld_r13_to_r23();
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void __ld_r13_to_r24();
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void __ld_r13_to_r25();
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void __adddf3();
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void __addsf3();
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void __divdf3();
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void __divdi3();
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void __divsf3();
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void __divsi3();
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void __eqsf2();
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void __extendsfdf2();
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void __fixdfsi();
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void __floatsidf();
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void __floatsisf();
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void __gedf2();
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void __gtdf2();
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void __ledf2();
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void __lesf2();
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void __ltdf2();
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void __muldf3();
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void __mulsf3();
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void __subdf3();
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void __subsf3();
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void __truncdfsf2();
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void __unorddf2();
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static SymbolMap target_sym_map[] = {
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REG_COMMON_SYMBOLS
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REG_SYM(__st_r13_to_r15),
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REG_SYM(__st_r13_to_r16),
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REG_SYM(__st_r13_to_r17),
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REG_SYM(__st_r13_to_r18),
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REG_SYM(__st_r13_to_r19),
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REG_SYM(__st_r13_to_r20),
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REG_SYM(__st_r13_to_r21),
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REG_SYM(__st_r13_to_r22),
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REG_SYM(__st_r13_to_r23),
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REG_SYM(__st_r13_to_r24),
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REG_SYM(__st_r13_to_r25),
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REG_SYM(__ld_r13_to_r15),
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REG_SYM(__ld_r13_to_r16),
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REG_SYM(__ld_r13_to_r17),
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REG_SYM(__ld_r13_to_r18),
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REG_SYM(__ld_r13_to_r19),
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REG_SYM(__ld_r13_to_r20),
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REG_SYM(__ld_r13_to_r21),
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REG_SYM(__ld_r13_to_r22),
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REG_SYM(__ld_r13_to_r23),
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REG_SYM(__ld_r13_to_r24),
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REG_SYM(__ld_r13_to_r25),
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REG_SYM (__adddf3),
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REG_SYM (__addsf3),
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REG_SYM (__divdf3),
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REG_SYM (__divdi3),
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REG_SYM (__divsf3),
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REG_SYM (__divsi3),
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REG_SYM (__eqsf2),
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REG_SYM (__extendsfdf2),
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REG_SYM (__fixdfsi),
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REG_SYM (__floatsidf),
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REG_SYM (__floatsisf),
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REG_SYM (__gedf2),
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REG_SYM (__gtdf2),
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REG_SYM (__ledf2),
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REG_SYM (__lesf2),
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REG_SYM (__ltdf2),
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REG_SYM (__muldf3),
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REG_SYM (__mulsf3),
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REG_SYM (__subdf3),
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REG_SYM (__subsf3),
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REG_SYM (__truncdfsf2),
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REG_SYM (__unorddf2),
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};
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static void
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set_error_buf(char *error_buf, uint32 error_buf_size, const char *string)
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{
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if (error_buf != NULL)
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snprintf(error_buf, error_buf_size, "%s", string);
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}
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SymbolMap *
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get_target_symbol_map(uint32 *sym_num)
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{
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*sym_num = sizeof(target_sym_map) / sizeof(SymbolMap);
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return target_sym_map;
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}
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void
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get_current_target(char *target_buf, uint32 target_buf_size)
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{
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snprintf(target_buf, target_buf_size, "arc");
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}
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uint32
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get_plt_table_size()
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{
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return 0;
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}
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void
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init_plt_table(uint8 *plt)
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{
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(void)plt;
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}
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static bool
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check_reloc_offset(uint32 target_section_size,
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uint64 reloc_offset, uint32 reloc_data_size,
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char *error_buf, uint32 error_buf_size)
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{
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if (!(reloc_offset < (uint64)target_section_size
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&& reloc_offset + reloc_data_size <= (uint64)target_section_size)) {
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set_error_buf(error_buf, error_buf_size,
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"AOT module load failed: invalid relocation offset.");
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return false;
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}
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return true;
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}
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static uint32
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middle_endian_convert(uint32 insn)
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{
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return ((insn & 0xFFFF0000) >> 16) | ((insn & 0x0000FFFF) << 16);
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}
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bool
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apply_relocation(AOTModule *module,
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uint8 *target_section_addr, uint32 target_section_size,
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uint64 reloc_offset, uint64 reloc_addend,
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uint32 reloc_type, void *symbol_addr, int32 symbol_index,
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char *error_buf, uint32 error_buf_size)
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{
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switch (reloc_type) {
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case R_ARC_S25W_PCREL:
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{
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uint32 insn = LOAD_I32(target_section_addr + reloc_offset);
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int32 addend, value;
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uintptr_t S, A, P;
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CHECK_RELOC_OFFSET(sizeof(void*));
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/* Convert from middle endian */
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insn = middle_endian_convert(insn);
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addend = ((insn << 28) >> 28) << 10;
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/* Extract the next 10 bits from Position 6 to 15 in insn */
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addend |= ((insn << 16) >> 22);
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addend = addend << 9;
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/* Extract the remaining 9 bits from Position 18 to 26 in insn */
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addend |= ((insn << 5) >> 23);
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/* Fill in 2 bits to get the 25 bit Offset Value */
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addend = addend << 2;
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/* (S + A) - P */
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S = (uintptr_t)(uint8*)symbol_addr;
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A = (uintptr_t)reloc_addend;
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P = (uintptr_t)(target_section_addr + reloc_offset);
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P &= (uintptr_t)~3;
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value = (int32)(S + A + addend - P);
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insn = insn & 0xf8030030;
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insn |= ((((value >> 2) & 0x1ff) << 18)
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| (((value >> 2) & 0x7fe00) >> 3)
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| (((value >> 2) & 0x780000) >> 19));
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/* Convert to middle endian */
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insn = middle_endian_convert(insn);
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STORE_U32(target_section_addr + reloc_offset, insn);
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break;
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}
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case R_ARC_32:
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case R_ARC_32_ME:
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{
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uint32 insn;
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CHECK_RELOC_OFFSET(sizeof(void*));
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/* (S + A) */
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insn = (uint32)(uintptr_t)
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((uint8*)symbol_addr + reloc_addend);
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if (reloc_type == R_ARC_32_ME)
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/* Convert to middle endian */
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insn = middle_endian_convert(insn);
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STORE_U32(target_section_addr + reloc_offset, insn);
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break;
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}
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default:
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{
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if (error_buf != NULL)
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snprintf(error_buf, error_buf_size,
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"Load relocation section failed: "
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"invalid relocation type %d.",
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reloc_type);
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return false;
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}
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}
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return true;
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}
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