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Refine build script of zephyr product-mini, enable aot soft-float support (#188)

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This commit is contained in:
wenyongh
2020-03-05 21:46:24 +08:00
committed by GitHub
parent be69c51aec
commit cfcaca3d35
10 changed files with 171 additions and 30 deletions
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30
core/iwasm/aot/arch/aot_reloc_arm.c
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@ -44,6 +44,20 @@ void __aeabi_idivmod();
void __aeabi_uidivmod();
void __aeabi_ldivmod();
void __aeabi_uldivmod();
void __aeabi_i2d();
void __aeabi_dadd();
void __aeabi_ddiv();
void __aeabi_dcmplt();
void __aeabi_dcmpun();
void __aeabi_dcmple();
void __aeabi_dcmpge();
void __aeabi_d2iz();
void __aeabi_fcmplt();
void __aeabi_fcmpun();
void __aeabi_fcmple();
void __aeabi_fcmpge();
void __aeabi_f2iz();
void __aeabi_f2d();
static SymbolMap target_sym_map[] = {
REG_COMMON_SYMBOLS,
@ -77,7 +91,21 @@ static SymbolMap target_sym_map[] = {
REG_SYM(__aeabi_idivmod),
REG_SYM(__aeabi_uidivmod),
REG_SYM(__aeabi_ldivmod),
REG_SYM(__aeabi_uldivmod)
REG_SYM(__aeabi_uldivmod),
REG_SYM(__aeabi_i2d),
REG_SYM(__aeabi_dadd),
REG_SYM(__aeabi_ddiv),
REG_SYM(__aeabi_dcmplt),
REG_SYM(__aeabi_dcmpun),
REG_SYM(__aeabi_dcmple),
REG_SYM(__aeabi_dcmpge),
REG_SYM(__aeabi_d2iz),
REG_SYM(__aeabi_fcmplt),
REG_SYM(__aeabi_fcmpun),
REG_SYM(__aeabi_fcmple),
REG_SYM(__aeabi_fcmpge),
REG_SYM(__aeabi_f2iz),
REG_SYM(__aeabi_f2d),
};
static void

30
core/iwasm/aot/arch/aot_reloc_thumb.c
View File

@ -43,6 +43,20 @@ void __aeabi_idivmod();
void __aeabi_uidivmod();
void __aeabi_ldivmod();
void __aeabi_uldivmod();
void __aeabi_i2d();
void __aeabi_dadd();
void __aeabi_ddiv();
void __aeabi_dcmplt();
void __aeabi_dcmpun();
void __aeabi_dcmple();
void __aeabi_dcmpge();
void __aeabi_d2iz();
void __aeabi_fcmplt();
void __aeabi_fcmpun();
void __aeabi_fcmple();
void __aeabi_fcmpge();
void __aeabi_f2iz();
void __aeabi_f2d();
static SymbolMap target_sym_map[] = {
REG_COMMON_SYMBOLS,
@ -76,7 +90,21 @@ static SymbolMap target_sym_map[] = {
REG_SYM(__aeabi_idivmod),
REG_SYM(__aeabi_uidivmod),
REG_SYM(__aeabi_ldivmod),
REG_SYM(__aeabi_uldivmod)
REG_SYM(__aeabi_uldivmod),
REG_SYM(__aeabi_i2d),
REG_SYM(__aeabi_dadd),
REG_SYM(__aeabi_ddiv),
REG_SYM(__aeabi_dcmplt),
REG_SYM(__aeabi_dcmpun),
REG_SYM(__aeabi_dcmple),
REG_SYM(__aeabi_dcmpge),
REG_SYM(__aeabi_d2iz),
REG_SYM(__aeabi_fcmplt),
REG_SYM(__aeabi_fcmpun),
REG_SYM(__aeabi_fcmple),
REG_SYM(__aeabi_fcmpge),
REG_SYM(__aeabi_f2iz),
REG_SYM(__aeabi_f2d),
};
static void

61
core/iwasm/compilation/aot_emit_numberic.c
View File

@ -857,13 +857,34 @@ fail:
return false;
}
static bool
is_targeting_soft_float(LLVMTargetMachineRef target_machine)
{
bool ret = false;
char *feature_string;
if (!(feature_string =
LLVMGetTargetMachineFeatureString(target_machine))) {
aot_set_last_error("llvm get target machine feature string fail.");
return false;
}
ret = strstr(feature_string, "+soft-float") ? true : false;
LLVMDisposeMessage(feature_string);
return ret;
}
static bool
compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
FloatArithmetic arith_op, bool is_f32)
{
switch (arith_op) {
case FLOAT_ADD:
DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
if (is_targeting_soft_float(comp_ctx->target_machine))
DEF_FP_BINARY_OP(LLVMBuildFAdd(comp_ctx->builder, left, right, "fadd"),
"llvm build fadd fail.");
else
DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
comp_ctx,
(is_f32
? "llvm.experimental.constrained.fadd.f32"
@ -873,10 +894,14 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
right,
comp_ctx->fp_rounding_mode,
comp_ctx->fp_exception_behavior),
NULL);
NULL);
return true;
case FLOAT_SUB:
DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
if (is_targeting_soft_float(comp_ctx->target_machine))
DEF_FP_BINARY_OP(LLVMBuildFSub(comp_ctx->builder, left, right, "fsub"),
"llvm build fsub fail.");
else
DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
comp_ctx,
(is_f32
? "llvm.experimental.constrained.fsub.f32"
@ -886,10 +911,14 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
right,
comp_ctx->fp_rounding_mode,
comp_ctx->fp_exception_behavior),
NULL);
NULL);
return true;
case FLOAT_MUL:
DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
if (is_targeting_soft_float(comp_ctx->target_machine))
DEF_FP_BINARY_OP(LLVMBuildFMul(comp_ctx->builder, left, right, "fmul"),
"llvm build fmul fail.");
else
DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
comp_ctx,
(is_f32
? "llvm.experimental.constrained.fmul.f32"
@ -899,10 +928,14 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
right,
comp_ctx->fp_rounding_mode,
comp_ctx->fp_exception_behavior),
NULL);
NULL);
return true;
case FLOAT_DIV:
DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
if (is_targeting_soft_float(comp_ctx->target_machine))
DEF_FP_BINARY_OP(LLVMBuildFDiv(comp_ctx->builder, left, right, "fdiv"),
"llvm build fdiv fail.");
else
DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
comp_ctx,
(is_f32
? "llvm.experimental.constrained.fdiv.f32"
@ -912,7 +945,7 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
right,
comp_ctx->fp_rounding_mode,
comp_ctx->fp_exception_behavior),
NULL);
NULL);
return true;
case FLOAT_MIN:
DEF_FP_BINARY_OP(compile_op_float_min_max(comp_ctx,
@ -1017,7 +1050,15 @@ compile_op_float_math(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
NULL);
return true;
case FLOAT_SQRT:
DEF_FP_UNARY_OP(call_llvm_libm_expermental_constrained_intrinsic(
if (is_targeting_soft_float(comp_ctx->target_machine))
DEF_FP_UNARY_OP(call_llvm_float_math_intrinsic(comp_ctx,
is_f32 ? "llvm.sqrt.f32" :
"llvm.sqrt.f64",
is_f32,
operand),
NULL);
else
DEF_FP_UNARY_OP(call_llvm_libm_expermental_constrained_intrinsic(
comp_ctx,
(is_f32
? "llvm.experimental.constrained.sqrt.f32"
@ -1026,7 +1067,7 @@ compile_op_float_math(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
operand,
comp_ctx->fp_rounding_mode,
comp_ctx->fp_exception_behavior),
NULL);
NULL);
return true;
default:
bh_assert(0);