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Add xtensa AOT support and fix build issue of alios (#223)

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* Clean compiling warnings of zephyr samples

* Support xtensa AOT and fix build issue of alios
This commit is contained in:
Weining
2020-04-01 18:38:42 +08:00
committed by GitHub
parent c1a0e6d877
commit c6fc12b7b6
20 changed files with 762 additions and 68 deletions
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38
core/iwasm/compilation/aot_emit_aot_file.c
View File

@ -49,6 +49,10 @@ typedef struct AOTObjectData {
void *text;
uint32 text_size;
/* literal data and size */
void *literal;
uint32 literal_size;
AOTObjectDataSection *data_sections;
uint32 data_sections_count;
@ -379,7 +383,7 @@ get_init_data_section_size(AOTCompData *comp_data, AOTObjectData *obj_data)
static uint32
get_text_section_size(AOTObjectData *obj_data)
{
return obj_data->text_size;
return (sizeof(uint32) + obj_data->literal_size + obj_data->text_size + 3) & ~3;
}
static uint32
@ -1118,13 +1122,20 @@ aot_emit_text_section(uint8 *buf, uint8 *buf_end, uint32 *p_offset,
{
uint32 section_size = get_text_section_size(obj_data);
uint32 offset = *p_offset;
uint8 placeholder = 0;
*p_offset = offset = align_uint(offset, 4);
EMIT_U32(AOT_SECTION_TYPE_TEXT);
EMIT_U32(section_size);
EMIT_U32(obj_data->literal_size);
if (obj_data->literal_size > 0)
EMIT_BUF(obj_data->literal, obj_data->literal_size);
EMIT_BUF(obj_data->text, obj_data->text_size);
while (offset & 3)
EMIT_BUF(&placeholder, 1);
if (offset - *p_offset != section_size + sizeof(uint32) * 2) {
aot_set_last_error("emit text section failed.");
return false;
@ -1449,6 +1460,29 @@ aot_resolve_text(AOTObjectData *obj_data)
return true;
}
static bool
aot_resolve_literal(AOTObjectData *obj_data)
{
LLVMSectionIteratorRef sec_itr;
char *name;
if (!(sec_itr = LLVMObjectFileCopySectionIterator(obj_data->binary))) {
aot_set_last_error("llvm get section iterator failed.");
return false;
}
while (!LLVMObjectFileIsSectionIteratorAtEnd(obj_data->binary, sec_itr)) {
if ((name = (char *)LLVMGetSectionName(sec_itr)) && !strcmp(name, ".literal")) {
obj_data->literal = (char *)LLVMGetSectionContents(sec_itr);
obj_data->literal_size = (uint32)LLVMGetSectionSize(sec_itr);
break;
}
LLVMMoveToNextSection(sec_itr);
}
LLVMDisposeSectionIterator(sec_itr);
return true;
}
static bool
is_data_section(char *section_name)
{
@ -1701,6 +1735,7 @@ is_relocation_section(char *section_name)
{
return (!strcmp(section_name, ".rela.text")
|| !strcmp(section_name, ".rel.text")
|| !strcmp(section_name, ".rela.literal")
|| !strcmp(section_name, ".rela.data")
|| !strcmp(section_name, ".rel.data")
|| !strcmp(section_name, ".rela.rodata")
@ -1873,6 +1908,7 @@ aot_obj_data_create(AOTCompContext *comp_ctx)
/* resolve target info/text/relocations/functions */
if (!aot_resolve_target_info(comp_ctx, obj_data)
|| !aot_resolve_text(obj_data)
|| !aot_resolve_literal(obj_data)
|| !aot_resolve_object_data_sections(obj_data)
|| !aot_resolve_object_relocation_groups(obj_data)
|| !aot_resolve_functions(comp_ctx, obj_data))

61
core/iwasm/compilation/aot_emit_numberic.c
View File

@ -858,18 +858,63 @@ fail:
}
static bool
is_targeting_soft_float(LLVMTargetMachineRef target_machine)
is_target_arm(AOTCompContext *comp_ctx)
{
return !strncmp(comp_ctx->target_arch, "arm", 3) ||
!strncmp(comp_ctx->target_arch, "thumb", 5);
}
static bool
is_target_x86(AOTCompContext *comp_ctx)
{
return !strncmp(comp_ctx->target_arch, "x86_64", 6) ||
!strncmp(comp_ctx->target_arch, "i386", 4);
}
static bool
is_target_xtensa(AOTCompContext *comp_ctx)
{
return !strncmp(comp_ctx->target_arch, "xtensa", 6);
}
static bool
is_target_mips(AOTCompContext *comp_ctx)
{
return !strncmp(comp_ctx->target_arch, "mips", 4);
}
static bool
is_targeting_soft_float(AOTCompContext *comp_ctx, bool is_f32)
{
bool ret = false;
char *feature_string;
if (!(feature_string =
LLVMGetTargetMachineFeatureString(target_machine))) {
LLVMGetTargetMachineFeatureString(comp_ctx->target_machine))) {
aot_set_last_error("llvm get target machine feature string fail.");
return false;
}
ret = strstr(feature_string, "+soft-float") ? true : false;
/* Note:
* LLVM CodeGen uses FPU Coprocessor registers by default,
* so user must specify '--cpu-features=+soft-float' to wamrc if the target
* doesn't have or enable FPU on arm, x86 or mips. */
if (is_target_arm(comp_ctx) ||
is_target_x86(comp_ctx) ||
is_target_mips(comp_ctx))
ret = strstr(feature_string, "+soft-float") ? true : false;
else if (is_target_xtensa(comp_ctx))
/* Note:
* 1. The Floating-Point Coprocessor Option of xtensa only support
* single-precision floating-point operations, so must use soft-float
* for f64(i.e. double).
* 2. LLVM CodeGen uses Floating-Point Coprocessor registers by default,
* so user must specify '--cpu-features=-fp' to wamrc if the target
* doesn't have or enable Floating-Point Coprocessor Option on xtensa. */
ret = (!is_f32 || strstr(feature_string, "-fp")) ? true : false;
else
ret = true;
LLVMDisposeMessage(feature_string);
return ret;
}
@ -880,7 +925,7 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
{
switch (arith_op) {
case FLOAT_ADD:
if (is_targeting_soft_float(comp_ctx->target_machine))
if (is_targeting_soft_float(comp_ctx, is_f32))
DEF_FP_BINARY_OP(LLVMBuildFAdd(comp_ctx->builder, left, right, "fadd"),
"llvm build fadd fail.");
else
@ -897,7 +942,7 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
NULL);
return true;
case FLOAT_SUB:
if (is_targeting_soft_float(comp_ctx->target_machine))
if (is_targeting_soft_float(comp_ctx, is_f32))
DEF_FP_BINARY_OP(LLVMBuildFSub(comp_ctx->builder, left, right, "fsub"),
"llvm build fsub fail.");
else
@ -914,7 +959,7 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
NULL);
return true;
case FLOAT_MUL:
if (is_targeting_soft_float(comp_ctx->target_machine))
if (is_targeting_soft_float(comp_ctx, is_f32))
DEF_FP_BINARY_OP(LLVMBuildFMul(comp_ctx->builder, left, right, "fmul"),
"llvm build fmul fail.");
else
@ -931,7 +976,7 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
NULL);
return true;
case FLOAT_DIV:
if (is_targeting_soft_float(comp_ctx->target_machine))
if (is_targeting_soft_float(comp_ctx, is_f32))
DEF_FP_BINARY_OP(LLVMBuildFDiv(comp_ctx->builder, left, right, "fdiv"),
"llvm build fdiv fail.");
else
@ -1050,7 +1095,7 @@ compile_op_float_math(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
NULL);
return true;
case FLOAT_SQRT:
if (is_targeting_soft_float(comp_ctx->target_machine))
if (is_targeting_soft_float(comp_ctx, is_f32))
DEF_FP_UNARY_OP(call_llvm_float_math_intrinsic(comp_ctx,
is_f32 ? "llvm.sqrt.f32" :
"llvm.sqrt.f64",

1
core/iwasm/compilation/aot_llvm.c
View File

@ -740,6 +740,7 @@ typedef struct ArchItem {
static ArchItem valid_archs[] = {
{ "x86_64", false },
{ "i386", false },
{ "xtensa", false},
{ "mips", true },
{ "aarch64v8", false },
{ "aarch64v8.1", false },