Import SIMD feature and add some workload samples (#438)
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64
core/iwasm/common/arch/invokeNative_em64_simd.s
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64
core/iwasm/common/arch/invokeNative_em64_simd.s
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/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*/
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.text
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.align 2
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#ifndef BH_PLATFORM_DARWIN
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.globl invokeNative
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.type invokeNative, @function
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invokeNative:
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#else
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.globl _invokeNative
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_invokeNative:
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#endif /* end of BH_PLATFORM_DARWIN */
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/* rdi - function ptr */
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/* rsi - argv */
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/* rdx - n_stacks */
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push %rbp
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mov %rsp, %rbp
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mov %rdx, %r10
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mov %rsp, %r11 /* Check that stack is aligned on */
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and $8, %r11 /* 16 bytes. This code may be removed */
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je check_stack_succ /* when we are sure that compiler always */
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int3 /* calls us with aligned stack */
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check_stack_succ:
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mov %r10, %r11 /* Align stack on 16 bytes before pushing */
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and $1, %r11 /* stack arguments in case we have an odd */
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shl $3, %r11 /* number of stack arguments */
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sub %r11, %rsp
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/* store memory args */
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movq %rdi, %r11 /* func ptr */
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movq %r10, %rcx /* counter */
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lea 128+48-8(%rsi,%rcx,8), %r10
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sub %rsp, %r10
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cmpq $0, %rcx
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je push_args_end
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push_args:
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push 0(%rsp,%r10)
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loop push_args
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push_args_end:
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/* fill all fp args */
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movdqa 0x00(%rsi), %xmm0
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movdqa 0x10(%rsi), %xmm1
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movdqa 0x20(%rsi), %xmm2
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movdqa 0x30(%rsi), %xmm3
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movdqa 0x40(%rsi), %xmm4
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movdqa 0x50(%rsi), %xmm5
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movdqa 0x60(%rsi), %xmm6
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movdqa 0x70(%rsi), %xmm7
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/* fill all int args */
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movq 0x80(%rsi), %rdi
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movq 0x90(%rsi), %rdx
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movq 0x98(%rsi), %rcx
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movq 0xa0(%rsi), %r8
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movq 0xa8(%rsi), %r9
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movq 0x88(%rsi), %rsi
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call *%r11
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leave
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ret
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