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Implement Fast JIT multi-threading feature (#2134)

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- Translate all the opcodes of threads spec proposal for Fast JIT
- Add the atomic flag for Fast JIT load/store IRs to support atomic load/store
- Add new atomic related Fast JIT IRs and translate them in the codegen
- Add suspend_flags check in branch opcodes and before/after call function
- Modify CI to enable Fast JIT multi-threading test

Co-authored-by: TianlongLiang <tianlong.liang@intel.com>
This commit is contained in:
Wenyong Huang
2023-04-20 10:09:34 +08:00
committed by GitHub
parent dfca21d239
commit 7e9bf9cdf5
15 changed files with 2290 additions and 168 deletions
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38
core/iwasm/fast-jit/jit_ir.h
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@ -313,7 +313,8 @@ typedef struct JitInsn {
/* Opcode of the instruction. */
uint16 opcode;
/* Reserved field that may be used by optimizations locally. */
/* Reserved field that may be used by optimizations locally.
* bit_0(Least Significant Bit) is atomic flag for load/store */
uint8 flags_u8;
/* The unique ID of the instruction. */
@ -346,6 +347,9 @@ typedef enum JitOpcode {
* Helper functions for creating new instructions. Don't call them
* directly. Use jit_insn_new_NAME, such as jit_insn_new_MOV instead.
*/
JitInsn *
_jit_insn_new_Reg_0(JitOpcode opc);
JitInsn *
_jit_insn_new_Reg_1(JitOpcode opc, JitReg r0);
JitInsn *
@ -368,31 +372,35 @@ _jit_insn_new_LookupSwitch_1(JitOpcode opc, JitReg value, uint32 num);
* Instruction creation functions jit_insn_new_NAME, where NAME is the
* name of the instruction defined in jit_ir.def.
*/
#define ARG_DECL_Reg_0
#define ARG_LIST_Reg_0
#define ARG_DECL_Reg_1 JitReg r0
#define ARG_LIST_Reg_1 r0
#define ARG_LIST_Reg_1 , r0
#define ARG_DECL_Reg_2 JitReg r0, JitReg r1
#define ARG_LIST_Reg_2 r0, r1
#define ARG_LIST_Reg_2 , r0, r1
#define ARG_DECL_Reg_3 JitReg r0, JitReg r1, JitReg r2
#define ARG_LIST_Reg_3 r0, r1, r2
#define ARG_LIST_Reg_3 , r0, r1, r2
#define ARG_DECL_Reg_4 JitReg r0, JitReg r1, JitReg r2, JitReg r3
#define ARG_LIST_Reg_4 r0, r1, r2, r3
#define ARG_LIST_Reg_4 , r0, r1, r2, r3
#define ARG_DECL_Reg_5 JitReg r0, JitReg r1, JitReg r2, JitReg r3, JitReg r4
#define ARG_LIST_Reg_5 r0, r1, r2, r3, r4
#define ARG_LIST_Reg_5 , r0, r1, r2, r3, r4
#define ARG_DECL_VReg_1 JitReg r0, int n
#define ARG_LIST_VReg_1 r0, n
#define ARG_LIST_VReg_1 , r0, n
#define ARG_DECL_VReg_2 JitReg r0, JitReg r1, int n
#define ARG_LIST_VReg_2 r0, r1, n
#define ARG_LIST_VReg_2 , r0, r1, n
#define ARG_DECL_LookupSwitch_1 JitReg value, uint32 num
#define ARG_LIST_LookupSwitch_1 value, num
#define INSN(NAME, OPND_KIND, OPND_NUM, FIRST_USE) \
static inline JitInsn *jit_insn_new_##NAME( \
ARG_DECL_##OPND_KIND##_##OPND_NUM) \
{ \
return _jit_insn_new_##OPND_KIND##_##OPND_NUM( \
JIT_OP_##NAME, ARG_LIST_##OPND_KIND##_##OPND_NUM); \
#define ARG_LIST_LookupSwitch_1 , value, num
#define INSN(NAME, OPND_KIND, OPND_NUM, FIRST_USE) \
static inline JitInsn *jit_insn_new_##NAME( \
ARG_DECL_##OPND_KIND##_##OPND_NUM) \
{ \
return _jit_insn_new_##OPND_KIND##_##OPND_NUM( \
JIT_OP_##NAME ARG_LIST_##OPND_KIND##_##OPND_NUM); \
}
#include "jit_ir.def"
#undef INSN
#undef ARG_DECL_Reg_0
#undef ARG_LIST_Reg_0
#undef ARG_DECL_Reg_1
#undef ARG_LIST_Reg_1
#undef ARG_DECL_Reg_2