Implement SIMD latest opcodes and update LLVM to 13.0 (#758)
Implement the latest SIMD opcodes and update LLVM 13.0, update the llvm build scripts, update the sample workloads‘ build scripts, and build customized wasi-sdk to build some workloads. Also refine the CI rules. Signed-off-by: Wenyong Huang <wenyong.huang@intel.com>
This commit is contained in:
Wenyong Huang
@ -296,18 +296,18 @@ typedef enum WASMMiscEXTOpcode {
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typedef enum WASMSimdEXTOpcode {
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/* memory instruction */
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SIMD_v128_load = 0x00,
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SIMD_i16x8_load8x8_s = 0x01,
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SIMD_i16x8_load8x8_u = 0x02,
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SIMD_i32x4_load16x4_s = 0x03,
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SIMD_i32x4_load16x4_u = 0x04,
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SIMD_i64x2_load32x2_s = 0x05,
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SIMD_i64x2_load32x2_u = 0x06,
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SIMD_v8x16_load_splat = 0x07,
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SIMD_v16x8_load_splat = 0x08,
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SIMD_v32x4_load_splat = 0x09,
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SIMD_v64x2_load_splat = 0x0a,
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SIMD_v128_store = 0x0b,
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SIMD_v128_load = 0x00,
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SIMD_v128_load8x8_s = 0x01,
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SIMD_v128_load8x8_u = 0x02,
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SIMD_v128_load16x4_s = 0x03,
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SIMD_v128_load16x4_u = 0x04,
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SIMD_v128_load32x2_s = 0x05,
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SIMD_v128_load32x2_u = 0x06,
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SIMD_v128_load8_splat = 0x07,
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SIMD_v128_load16_splat = 0x08,
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SIMD_v128_load32_splat = 0x09,
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SIMD_v128_load64_splat = 0x0a,
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SIMD_v128_store = 0x0b,
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/* basic operation */
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SIMD_v128_const = 0x0c,
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@ -391,107 +391,170 @@ typedef enum WASMSimdEXTOpcode {
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SIMD_f64x2_ge = 0x4c,
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/* v128 operation */
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SIMD_v128_not = 0x4d,
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SIMD_v128_and = 0x4e,
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SIMD_v128_andnot = 0x4f,
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SIMD_v128_or = 0x50,
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SIMD_v128_xor = 0x51,
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SIMD_v128_not = 0x4d,
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SIMD_v128_and = 0x4e,
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SIMD_v128_andnot = 0x4f,
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SIMD_v128_or = 0x50,
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SIMD_v128_xor = 0x51,
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SIMD_v128_bitselect = 0x52,
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SIMD_v128_any_true = 0x53,
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/* Load Lane Operation */
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SIMD_v128_load8_lane = 0x54,
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SIMD_v128_load16_lane = 0x55,
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SIMD_v128_load32_lane = 0x56,
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SIMD_v128_load64_lane = 0x57,
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SIMD_v128_store8_lane = 0x58,
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SIMD_v128_store16_lane = 0x59,
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SIMD_v128_store32_lane = 0x5a,
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SIMD_v128_store64_lane = 0x5b,
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SIMD_v128_load32_zero = 0x5c,
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SIMD_v128_load64_zero = 0x5d,
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/* Float conversion */
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SIMD_f32x4_demote_f64x2_zero = 0x5e,
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SIMD_f64x2_promote_low_f32x4_zero = 0x5f,
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/* i8x16 Operation */
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SIMD_i8x16_abs = 0x60,
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SIMD_i8x16_neg = 0x61,
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SIMD_i8x16_any_true = 0x62,
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SIMD_i8x16_popcnt = 0x62,
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SIMD_i8x16_all_true = 0x63,
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SIMD_i8x16_bitmask = 0x64,
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SIMD_i8x16_narrow_i16x8_s = 0x65,
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SIMD_i8x16_narrow_i16x8_u = 0x66,
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SIMD_f32x4_ceil = 0x67,
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SIMD_f32x4_floor = 0x68,
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SIMD_f32x4_trunc = 0x69,
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SIMD_f32x4_nearest = 0x6a,
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SIMD_i8x16_shl = 0x6b,
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SIMD_i8x16_shr_s = 0x6c,
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SIMD_i8x16_shr_u = 0x6d,
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SIMD_i8x16_add = 0x6e,
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SIMD_i8x16_add_saturate_s = 0x6f,
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SIMD_i8x16_add_saturate_u = 0x70,
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SIMD_i8x16_add_sat_s = 0x6f,
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SIMD_i8x16_add_sat_u = 0x70,
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SIMD_i8x16_sub = 0x71,
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SIMD_i8x16_sub_saturate_s = 0x72,
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SIMD_i8x16_sub_saturate_u = 0x73,
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SIMD_i8x16_sub_sat_s = 0x72,
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SIMD_i8x16_sub_sat_u = 0x73,
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SIMD_f64x2_ceil = 0x74,
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SIMD_f64x2_floor = 0x75,
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SIMD_i8x16_min_s = 0x76,
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SIMD_i8x16_min_u = 0x77,
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SIMD_i8x16_max_s = 0x78,
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SIMD_i8x16_max_u = 0x79,
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SIMD_f64x2_trunc = 0x7a,
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SIMD_i8x16_avgr_u = 0x7b,
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SIMD_i16x8_extadd_pairwise_i8x16_s = 0x7c,
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SIMD_i16x8_extadd_pairwise_i8x16_u = 0x7d,
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SIMD_i32x4_extadd_pairwise_i16x8_s = 0x7e,
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SIMD_i32x4_extadd_pairwise_i16x8_u = 0x7f,
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/* i16x8 operation */
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SIMD_i16x8_abs = 0x80,
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SIMD_i16x8_neg = 0x81,
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SIMD_i16x8_any_true = 0x82,
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SIMD_i16x8_q15mulr_sat_s = 0x82,
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SIMD_i16x8_all_true = 0x83,
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SIMD_i16x8_bitmask = 0x84,
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SIMD_i16x8_narrow_i32x4_s = 0x85,
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SIMD_i16x8_narrow_i32x4_u = 0x86,
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SIMD_i16x8_widen_low_i8x16_s = 0x87,
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SIMD_i16x8_widen_high_i8x16_s = 0x88,
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SIMD_i16x8_widen_low_i8x16_u = 0x89,
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SIMD_i16x8_widen_high_i8x16_u = 0x8a,
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SIMD_i16x8_extend_low_i8x16_s = 0x87,
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SIMD_i16x8_extend_high_i8x16_s = 0x88,
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SIMD_i16x8_extend_low_i8x16_u = 0x89,
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SIMD_i16x8_extend_high_i8x16_u = 0x8a,
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SIMD_i16x8_shl = 0x8b,
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SIMD_i16x8_shr_s = 0x8c,
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SIMD_i16x8_shr_u = 0x8d,
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SIMD_i16x8_add = 0x8e,
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SIMD_i16x8_add_saturate_s = 0x8f,
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SIMD_i16x8_add_saturate_u = 0x90,
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SIMD_i16x8_add_sat_s = 0x8f,
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SIMD_i16x8_add_sat_u = 0x90,
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SIMD_i16x8_sub = 0x91,
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SIMD_i16x8_sub_saturate_s = 0x92,
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SIMD_i16x8_sub_saturate_u = 0x93,
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SIMD_i16x8_sub_sat_s = 0x92,
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SIMD_i16x8_sub_sat_u = 0x93,
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SIMD_f64x2_nearest = 0x94,
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SIMD_i16x8_mul = 0x95,
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SIMD_i16x8_min_s = 0x96,
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SIMD_i16x8_min_u = 0x97,
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SIMD_i16x8_max_s = 0x98,
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SIMD_i16x8_max_u = 0x99,
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/* placeholder = 0x9a */
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SIMD_i16x8_avgr_u = 0x9b,
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SIMD_i16x8_extmul_low_i8x16_s = 0x9c,
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SIMD_i16x8_extmul_high_i8x16_s = 0x9d,
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SIMD_i16x8_extmul_low_i8x16_u = 0x9e,
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SIMD_i16x8_extmul_high_i8x16_u = 0x9f,
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/* i32x4 operation */
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SIMD_i32x4_abs = 0xa0,
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SIMD_i32x4_neg = 0xa1,
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SIMD_i32x4_any_true = 0xa2,
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/* placeholder = 0xa2 */
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SIMD_i32x4_all_true = 0xa3,
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SIMD_i32x4_bitmask = 0xa4,
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SIMD_i32x4_widen_low_i16x8_s = 0xa7,
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SIMD_i32x4_widen_high_i16x8_s = 0xa8,
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SIMD_i32x4_widen_low_i16x8_u = 0xa9,
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SIMD_i32x4_widen_high_i16x8_u = 0xaa,
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SIMD_i32x4_narrow_i64x2_s = 0xa5,
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SIMD_i32x4_narrow_i64x2_u = 0xa6,
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SIMD_i32x4_extend_low_i16x8_s = 0xa7,
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SIMD_i32x4_extend_high_i16x8_s = 0xa8,
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SIMD_i32x4_extend_low_i16x8_u = 0xa9,
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SIMD_i32x4_extend_high_i16x8_u = 0xaa,
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SIMD_i32x4_shl = 0xab,
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SIMD_i32x4_shr_s = 0xac,
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SIMD_i32x4_shr_u = 0xad,
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SIMD_i32x4_add = 0xae,
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SIMD_i32x4_add_sat_s = 0xaf,
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SIMD_i32x4_add_sat_u = 0xb0,
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SIMD_i32x4_sub = 0xb1,
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SIMD_i32x4_sub_sat_s = 0xb2,
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SIMD_i32x4_sub_sat_u = 0xb3,
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/* placeholder = 0xb4 */
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SIMD_i32x4_mul = 0xb5,
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SIMD_i32x4_min_s = 0xb6,
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SIMD_i32x4_min_u = 0xb7,
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SIMD_i32x4_max_s = 0xb8,
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SIMD_i32x4_max_u = 0xb9,
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SIMD_i32x4_dot_i16x8_s = 0xba,
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SIMD_i32x4_avgr_u = 0xbb,
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SIMD_i32x4_extmul_low_i16x8_s = 0xbc,
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SIMD_i32x4_extmul_high_i16x8_s = 0xbd,
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SIMD_i32x4_extmul_low_i16x8_u = 0xbe,
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SIMD_i32x4_extmul_high_i16x8_u = 0xbf,
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/* i64x2 operation */
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SIMD_i64x2_neg = 0xc1,
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SIMD_i64x2_shl = 0xcb,
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SIMD_i64x2_shr_s = 0xcc,
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SIMD_i64x2_shr_u = 0xcd,
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SIMD_i64x2_add = 0xce,
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SIMD_i64x2_sub = 0xd1,
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SIMD_i64x2_mul = 0xd5,
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/* float ceil/floor/trunc/nearest */
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SIMD_f32x4_ceil = 0xd8,
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SIMD_f32x4_floor = 0xd9,
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SIMD_f32x4_trunc = 0xda,
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SIMD_f32x4_nearest = 0xdb,
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SIMD_f64x2_ceil = 0xdc,
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SIMD_f64x2_floor = 0xdd,
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SIMD_f64x2_trunc = 0xde,
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SIMD_f64x2_nearest = 0xdf,
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SIMD_i64x2_abs = 0xc0,
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SIMD_i64x2_neg = 0xc1,
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/* placeholder = 0xc2 */
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SIMD_i64x2_all_true = 0xc3,
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SIMD_i64x2_bitmask = 0xc4,
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/* placeholder = 0xc5 */
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/* placeholder = 0xc6 */
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SIMD_i64x2_extend_low_i32x4_s = 0xc7,
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SIMD_i64x2_extend_high_i32x4_s = 0xc8,
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SIMD_i64x2_extend_low_i32x4_u = 0xc9,
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SIMD_i64x2_extend_high_i32x4_u = 0xca,
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SIMD_i64x2_shl = 0xcb,
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SIMD_i64x2_shr_s = 0xcc,
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SIMD_i64x2_shr_u = 0xcd,
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SIMD_i64x2_add = 0xce,
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/* placeholder = 0xcf */
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/* placeholder = 0xd0 */
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SIMD_i64x2_sub = 0xd1,
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/* placeholder = 0xd2 */
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/* placeholder = 0xd3 */
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/* placeholder = 0xd4 */
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SIMD_i64x2_mul = 0xd5,
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SIMD_i64x2_eq = 0xd6,
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SIMD_i64x2_ne = 0xd7,
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SIMD_i64x2_lt_s = 0xd8,
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SIMD_i64x2_gt_s = 0xd9,
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SIMD_i64x2_le_s = 0xda,
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SIMD_i64x2_ge_s = 0xdb,
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SIMD_i64x2_extmul_low_i32x4_s = 0xdc,
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SIMD_i64x2_extmul_high_i32x4_s = 0xdd,
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SIMD_i64x2_extmul_low_i32x4_u = 0xde,
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SIMD_i64x2_extmul_high_i32x4_u = 0xdf,
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/* f32x4 operation */
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SIMD_f32x4_abs = 0xe0,
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SIMD_f32x4_neg = 0xe1,
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SIMD_f32x4_round = 0xe2,
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SIMD_f32x4_sqrt = 0xe3,
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SIMD_f32x4_add = 0xe4,
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SIMD_f32x4_sub = 0xe5,
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@ -499,10 +562,13 @@ typedef enum WASMSimdEXTOpcode {
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SIMD_f32x4_div = 0xe7,
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SIMD_f32x4_min = 0xe8,
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SIMD_f32x4_max = 0xe9,
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SIMD_f32x4_pmin = 0xea,
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SIMD_f32x4_pmax = 0xeb,
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/* f64x2 operation */
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SIMD_f64x2_abs = 0xec,
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SIMD_f64x2_neg = 0xed,
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SIMD_f64x2_round = 0xee,
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SIMD_f64x2_sqrt = 0xef,
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SIMD_f64x2_add = 0xf0,
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SIMD_f64x2_sub = 0xf1,
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@ -510,12 +576,18 @@ typedef enum WASMSimdEXTOpcode {
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SIMD_f64x2_div = 0xf3,
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SIMD_f64x2_min = 0xf4,
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SIMD_f64x2_max = 0xf5,
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SIMD_f64x2_pmin = 0xf6,
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SIMD_f64x2_pmax = 0xf7,
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/* conversion operation */
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SIMD_i32x4_trunc_sat_f32x4_s = 0xf8,
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SIMD_i32x4_trunc_sat_f32x4_u = 0xf9,
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SIMD_f32x4_convert_i32x4_s = 0xfa,
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SIMD_f32x4_convert_i32x4_u = 0xfb,
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SIMD_i32x4_trunc_sat_f32x4_s = 0xf8,
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SIMD_i32x4_trunc_sat_f32x4_u = 0xf9,
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SIMD_f32x4_convert_i32x4_s = 0xfa,
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SIMD_f32x4_convert_i32x4_u = 0xfb,
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SIMD_i32x4_trunc_sat_f64x2_s_zero = 0xfc,
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SIMD_i32x4_trunc_sat_f64x2_u_zero = 0xfd,
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SIMD_f64x2_convert_low_i32x4_s = 0xfe,
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SIMD_f64x2_convert_low_i32x4_u = 0xff,
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} WASMSimdEXTOpcode;
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typedef enum WASMAtomicEXTOpcode {
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