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fix: correct typos and improve comments across multiple files by codespell (#4116)

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
2025-03-07 08:21:54 +08:00
committed by GitHub
parent 73998e4c85
commit 412631ac13
108 changed files with 215 additions and 215 deletions
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20
core/iwasm/fast-jit/cg/x86-64/jit_codegen_x86_64.cpp
View File

@ -423,7 +423,7 @@ jmp_from_label_to_label(x86::Assembler &a, bh_list *jmp_info_list,
/**
* Encode detecting compare result register according to condition code
* and then jumping to suitable label when the condtion is met
* and then jumping to suitable label when the condition is met
*
* @param cc the compiler context
* @param a the assembler to emit the code
@ -431,7 +431,7 @@ jmp_from_label_to_label(x86::Assembler &a, bh_list *jmp_info_list,
* @param label_src the index of src label
* @param op the opcode of condition operation
* @param r1 the label info when condition is met
* @param r2 the label info when condition is unmet, do nonthing if VOID
* @param r2 the label info when condition is unmet, do nothing if VOID
* @param is_last_insn if current insn is the last insn of current block
*
* @return true if success, false if failed
@ -2589,7 +2589,7 @@ alu_r_r_r_i32(x86::Assembler &a, ALU_OP op, int32 reg_no_dst, int32 reg_no1_src,
if (reg_no2_src == REG_EDX_IDX) {
/* convert `REM_S edx, eax, edx` into
`mov esi, edx` and `REM_S edx eax, rsi` to
avoid overwritting edx when a.cdq() */
avoid overwriting edx when a.cdq() */
a.mov(regs_i32[REG_I32_FREE_IDX], regs_i32[REG_EDX_IDX]);
reg_no2_src = REG_I32_FREE_IDX;
}
@ -2609,7 +2609,7 @@ alu_r_r_r_i32(x86::Assembler &a, ALU_OP op, int32 reg_no_dst, int32 reg_no1_src,
if (reg_no2_src == REG_EDX_IDX) {
/* convert `REM_U edx, eax, edx` into
`mov esi, edx` and `REM_U edx eax, rsi` to
avoid overwritting edx when unsigned extend
avoid overwriting edx when unsigned extend
eax to edx:eax */
a.mov(regs_i32[REG_I32_FREE_IDX], regs_i32[REG_EDX_IDX]);
reg_no2_src = REG_I32_FREE_IDX;
@ -5602,7 +5602,7 @@ fail:
a.jmp(imm); \
if (!err_handler->err) { \
/* The offset written by asmjit is always 0, we patch it \
again, 6 is the size of jmp instruciton */ \
again, 6 is the size of jmp instruction */ \
stream = (char *)a.code()->sectionById(0)->buffer().data() \
+ a.code()->sectionById(0)->buffer().size() - 6; \
_offset = label_offsets[label_dst] \
@ -6169,7 +6169,7 @@ fail:
* Replace all the jmp address pre-saved when the code cache hasn't been
* allocated with actual address after code cache allocated
*
* @param cc compiler context containting the allocated code cacha info
* @param cc compiler context containing the allocated code cacha info
* @param jmp_info_list the jmp info list
*/
static void
@ -6557,7 +6557,7 @@ at_cmpxchg_r_ra_base_r_offset_imm(x86::Assembler &a, uint32 bytes_dst,
* @param a the assembler to emit the code
* @param bytes_dst the bytes number of the data to actual operated on(load,
* compare, replacement) could be 1(byte), 2(short), 4(int32), 8(int64)
* @param data_xchg the immediate data for exchange(conditionally replacment
* @param data_xchg the immediate data for exchange(conditionally replacement
* value)
* @param reg_no_base the no of register that stores the base address
* of src&dst memory
@ -6587,7 +6587,7 @@ at_cmpxchg_imm_ra_base_r_offset_r(x86::Assembler &a, uint32 bytes_dst,
* @param a the assembler to emit the code
* @param bytes_dst the bytes number of the data to actual operated on(load,
* compare, replacement) could be 1(byte), 2(short), 4(int32), 8(int64)
* @param data_xchg the immediate data for exchange(conditionally replacment
* @param data_xchg the immediate data for exchange(conditionally replacement
* value)
* @param reg_no_base the no of register that stores the base address
* of src&dst memory
@ -8820,7 +8820,7 @@ jit_codegen_compile_call_to_fast_jit(const WASMModule *module, uint32 func_idx)
/* If yes, set eax to 0, return to caller */
/* Pop all integer arument registers */
/* Pop all integer argument registers */
for (i = 0; i < MAX_REG_INTS; i++) {
a.pop(regs_i64[reg_idx_of_int_args[i]]);
}
@ -9084,7 +9084,7 @@ jit_codegen_compile_call_to_fast_jit(const WASMModule *module, uint32 func_idx)
a.mov(m, x86::rdx);
}
/* Pop all integer arument registers */
/* Pop all integer argument registers */
for (i = 0; i < MAX_REG_INTS; i++) {
a.pop(regs_i64[reg_idx_of_int_args[i]]);
}

2
core/iwasm/fast-jit/fe/jit_emit_compare.c
View File

@ -14,7 +14,7 @@ jit_compile_op_compare_integer(JitCompContext *cc, IntCond cond, bool is64Bit)
JitReg lhs, rhs, res, const_zero, const_one;
if (cond < INT_EQZ || cond > INT_GE_U) {
jit_set_last_error(cc, "unsupported comparation operation");
jit_set_last_error(cc, "unsupported comparison operation");
goto fail;
}

2
core/iwasm/fast-jit/fe/jit_emit_control.c
View File

@ -1230,7 +1230,7 @@ jit_compile_op_br_table(JitCompContext *cc, uint32 *br_depths, uint32 br_count,
copy_arities = check_copy_arities(block_dst, cc->jit_frame);
if (!copy_arities) {
/* No need to create new basic block, direclty jump to
/* No need to create new basic block, directly jump to
the existing basic block when no need to copy arities */
if (i == br_count) {
if (block_dst->label_type == LABEL_TYPE_LOOP) {

4
core/iwasm/fast-jit/jit_frontend.c
View File

@ -31,7 +31,7 @@ get_global_base_offset(const WASMModule *module)
* (module->import_memory_count + module->memory_count);
#if WASM_ENABLE_JIT != 0
/* If the module dosen't have memory, reserve one mem_info space
/* If the module doesn't have memory, reserve one mem_info space
with empty content to align with llvm jit compiler */
if (mem_inst_size == 0)
mem_inst_size = (uint32)sizeof(WASMMemoryInstance);
@ -1169,7 +1169,7 @@ init_func_translation(JitCompContext *cc)
time_started = jit_cc_new_reg_I64(cc);
/* Call os_time_thread_cputime_us() to get time_started firstly
as there is stack frame switching below, calling native in them
may cause register spilling work inproperly */
may cause register spilling work improperly */
if (!jit_emit_callnative(cc, os_time_thread_cputime_us, time_started, NULL,
0)) {
return NULL;

10
core/iwasm/fast-jit/jit_ir.h
View File

@ -94,7 +94,7 @@ typedef uint32 JitReg;
/*
* Constant index flag of non-constant-value (constant value flag is
* not set in register no. field) integer, floating point and vector
* regisers. If this flag is set, the rest bits of the register
* registers. If this flag is set, the rest bits of the register
* no. represent an index to the constant value table of the
* corresponding type of the register and the register is read-only.
*/
@ -1084,7 +1084,7 @@ typedef struct JitCompContext {
/* Capacity of register annotations of each kind. */
uint32 _capacity[JIT_REG_KIND_L32];
/* Constant vallues of each kind. */
/* Constant values of each kind. */
uint8 *_value[JIT_REG_KIND_L32];
/* Next element on the list of values with the same hash code. */
@ -1145,7 +1145,7 @@ typedef struct JitCompContext {
JitInsn **_table;
} _insn_hash_table;
/* indicate if the last comparision is about floating-point numbers or not
/* indicate if the last comparison is about floating-point numbers or not
*/
bool last_cmp_on_fp;
} JitCompContext;
@ -1203,7 +1203,7 @@ typedef struct JitCompContext {
* Annotation disabling functions jit_annl_disable_NAME,
* jit_anni_disable_NAME and jit_annr_disable_NAME, which release
* memory of the annotations. Before calling these functions,
* resources owned by the annotations must be explictely released.
* resources owned by the annotations must be explicitly released.
*/
#define ANN_LABEL(TYPE, NAME) void jit_annl_disable_##NAME(JitCompContext *cc);
#define ANN_INSN(TYPE, NAME) void jit_anni_disable_##NAME(JitCompContext *cc);
@ -1559,7 +1559,7 @@ _jit_cc_new_insn_norm(JitCompContext *cc, JitReg *result, JitInsn *insn);
*
* @param cc the compilationo context
* @param result returned result of the instruction. If the value is
* non-zero, it is the result of the constant-folding or an exsiting
* non-zero, it is the result of the constant-folding or an existing
* equivalent instruction, in which case no instruction is added into
* the compilation context. Otherwise, a new normalized instruction
* has been added into the compilation context.

8
core/iwasm/fast-jit/jit_regalloc.c
View File

@ -221,7 +221,7 @@ get_reg_stride(JitReg reg)
* @param rc the regalloc context
* @param vreg the virtual register
*
* @return the spill slot encoded in a consant register
* @return the spill slot encoded in a constant register
*/
static JitReg
rc_alloc_spill_slot(RegallocContext *rc, JitReg vreg)
@ -478,7 +478,7 @@ reload_vreg(RegallocContext *rc, JitReg vreg, JitInsn *cur_insn)
JitReg fp_reg = rc->cc->fp_reg, offset;
if (!vr->slot && !(vr->slot = rc_alloc_spill_slot(rc, vreg)))
/* Cannot allocte spill slot (due to OOM or frame size limit). */
/* Cannot allocate spill slot (due to OOM or frame size limit). */
return NULL;
offset = offset_of_spill_slot(rc->cc, vr->slot);
@ -579,7 +579,7 @@ spill_vreg(RegallocContext *rc, JitReg vreg, JitInsn *cur_insn)
/**
* Allocate a hard register for the virtual register. Necessary
* reloade instruction will be inserted after the given instruction.
* reload instruction will be inserted after the given instruction.
*
* @param rc the regalloc context
* @param vreg the virtual register
@ -665,7 +665,7 @@ allocate_hreg(RegallocContext *rc, JitReg vreg, JitInsn *insn, int distance)
/**
* Allocate a hard register for the virtual register if not allocated
* yet. Necessary spill and reloade instructions will be inserted
* yet. Necessary spill and reload instructions will be inserted
* before/after and after the given instruction. This operation will
* convert the virtual register's state from 1 or 3 to 2.
*