67 lines
1.4 KiB
Systemverilog
67 lines
1.4 KiB
Systemverilog
`default_nettype none
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module ArithmeticUnit_TestBench;
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var logic[2:0] opcode;
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var logic signed[7:0] operandA;
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var logic signed[7:0] operandB;
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tri signed[7:0] result;
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ArithmeticUnit au(
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.opcode(opcode),
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.operandA(operandA),
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.operandB(operandB),
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.result(result)
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);
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// synthesis translate_off
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initial begin
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$timeformat(-9, 2, " ns", 20);
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$display("%0t Initial Reset", $time);
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opcode = 3'b000;
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operandA = 8'b00000000;
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operandB = 8'b00000000;
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#20 assert(result == 8'b00000000);
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// First set of operands
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operandA = 8'b00000000;
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operandB = 8'b01010101;
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$display("%0t ADD 1", $time);
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opcode = 3'b100;
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#20 assert(result == 8'b01010101);
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$display("%0t SUB 1", $time);
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opcode = 3'b101;
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#20 assert(result == 8'b10101011);
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// Second set of operands
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operandA = 8'b11111111;
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operandB = 8'b01010101;
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$display("%0t ADD 2", $time);
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opcode = 3'b100;
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#20 assert(result == 8'b01010100); // With carry, we don't have flags yet
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$display("%0t SUB 2", $time);
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opcode = 3'b101;
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#20 assert(result == 8'b10101010);
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// Third set of operands
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operandA = 8'b00001111;
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operandB = 8'b01010101;
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$display("%0t ADD 3", $time);
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opcode = 3'b100;
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#20 assert(result == 8'b01100100);
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$display("%0t SUB 3", $time);
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opcode = 3'b101;
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#20 assert(result == 8'b10111010);
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$display("Success!");
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end
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// synthesis translate_on
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endmodule |