150 lines
3.8 KiB
Systemverilog
150 lines
3.8 KiB
Systemverilog
`default_nettype none
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module CPU_TestBench;
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var logic enable, clock, reset;
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var logic[7:0] cpuin;
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tri[7:0] cpuout;
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// Debug connections
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tri ftch, decd, exec, wrtb;
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tri[7:0] pc, rom, saveb, loadb, jmpt, aluA, aluB, aluR;
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CPU cpu(
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.enable(enable),
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.clock(clock),
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.reset(reset),
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.cpuin(cpuin),
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.cpuout(cpuout),
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.dbg_fetch(ftch),
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.dbg_decode(decd),
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.dbg_execute(exec),
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.dbg_writeback(wrtb),
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.dbg_pcout(pc),
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.dbg_romout(rom),
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.dbg_savebus(saveb),
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.dbg_loadbus(loadb),
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.dbg_jumptarget(jmpt),
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.dbg_aluopA(aluA),
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.dbg_aluopB(aluB),
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.dbg_aluresult(aluR)
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);
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// TODO: Move the disabled stuff to a separate testbench
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// TODO: Move this to a ROM specific testbench, allow creating other ROM specific testbenches
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// NOTE: This testbench is written for the Input/Output ROM
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// synthesis translate_off
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integer ii;
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initial begin
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$timeformat(-9, 2, " ns", 20);
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$display("%0t Initial Reset", $time);
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enable = 1'b0;
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clock = 1'b0;
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#20 reset = 1'b1;
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#20 reset = 1'b0;
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assert(cpuout == 8'b0);
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// $display("%0t Disabled CPU with Clock", $time);
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// for (ii = 0; ii < 4; ii = ii + 1) begin
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// #20 clock = 1'b1;
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// #20 clock = 1'b0;
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// assert(ftch == 1'b0);
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// assert(decd == 1'b0);
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// assert(exec == 1'b0);
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// assert(wrtb == 1'b0);
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// end
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$display("%0t Enable CPU", $time);
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#20 enable = 1'b1;
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#20 cpuin = 8'b00000101;
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// $display("%0t Clock => Fetch 1", $time);
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// #20 clock = 1'b1;
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// #20 clock = 1'b0;
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// assert(ftch == 1'b1);
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// assert(decd == 1'b0);
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// assert(exec == 1'b0);
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// assert(wrtb == 1'b0);
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// $display("%0t Clock => Decode 1", $time);
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// #20 clock = 1'b1;
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// #20 clock = 1'b0;
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// assert(ftch == 1'b0);
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// assert(decd == 1'b1);
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// assert(exec == 1'b0);
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// assert(wrtb == 1'b0);
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// $display("%0t Clock => Execute 1", $time);
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// #20 clock = 1'b1;
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// #20 clock = 1'b0;
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// assert(ftch == 1'b0);
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// assert(decd == 1'b0);
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// assert(exec == 1'b1);
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// assert(wrtb == 1'b0);
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// $display("%0t Clock => Writeback 1", $time);
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// #20 clock = 1'b1;
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// #20 clock = 1'b0;
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// assert(ftch == 1'b0);
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// assert(decd == 1'b0);
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// assert(exec == 1'b0);
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// assert(wrtb == 1'b1);
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// Next CPU cycle (reg1 = cpuin)
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$display("%0t reg1 (aluA) = cpuin", $time);
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for (ii = 0; ii < 4; ii = ii + 1) begin
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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end
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assert(aluA == 8'b00000101);
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// Next CPU cycle (reg0 = 10)
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$display("%0t reg0 (jmpt) = 00001010", $time);
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for (ii = 0; ii < 4; ii = ii + 1) begin
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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end
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assert(jmpt == 8'b00001010);
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assert(aluA == 8'b00000101);
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// Next CPU cycle (reg2 = reg0)
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$display("%0t reg2 (aluB) = reg0 (jmpt)", $time);
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for (ii = 0; ii < 4; ii = ii + 1) begin
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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end
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assert(jmpt == 8'b00001010);
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assert(aluA == 8'b00000101);
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assert(aluB == 8'b00001010);
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// Next CPU cycle (reg3 = reg1 + reg2)
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$display("%0t reg3 (aluR) = reg1 (aluA) + reg2 (aluB)", $time);
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for (ii = 0; ii < 4; ii = ii + 1) begin
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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end
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assert(jmpt == 8'b00001010);
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assert(aluA == 8'b00000101);
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assert(aluB == 8'b00001010);
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assert(aluR == 8'b00001111);
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// Next CPU cycle (cpuout = reg3)
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$display("%0t cpuout = reg3 (aluR)", $time);
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for (ii = 0; ii < 4; ii = ii + 1) begin
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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end
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assert(jmpt == 8'b00001010);
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assert(aluA == 8'b00000101);
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assert(aluB == 8'b00001010);
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assert(aluR == 8'b00001111);
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assert(cpuout == 8'b00001111);
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$display("Success!");
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end
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// synthesis translate_on
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endmodule |