24 lines
594 B
Systemverilog
24 lines
594 B
Systemverilog
`default_nettype none
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// Inst: MD OP
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// 01 000 XXX
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// OPs: 000 - AND
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// 001 - OR
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// 010 - NAND
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// 011 - NOR
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module LogicalUnit(
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input var logic[2:0] opcode,
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input var logic[7:0] operandA,
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input var logic[7:0] operandB,
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output var logic[7:0] result
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);
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always @(opcode or operandA or operandB) case (opcode)
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3'b000: result = operandA & operandB;
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3'b001: result = operandA | operandB;
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3'b010: result = ~(operandA & operandB);
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3'b011: result = ~(operandA | operandB);
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default: result = 0;
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endcase
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endmodule
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