23 lines
499 B
Systemverilog
23 lines
499 B
Systemverilog
`default_nettype none
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module Counter(
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input var logic clock,
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input var logic reset,
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input var logic decrement,
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input var logic setvalue,
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input var logic[7:0] valuein,
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output var logic[7:0] valueout
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);
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var logic[7:0] countervalue;
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always @(posedge clock or posedge reset)
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if (reset)
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countervalue <= 8'b0;
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else if (setvalue)
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countervalue <= valuein;
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else
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countervalue <= countervalue + (decrement ? -1 : 1);
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assign valueout = countervalue;
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endmodule |