45 lines
921 B
Systemverilog
45 lines
921 B
Systemverilog
`default_nettype none
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// Inst: MD OP
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// 01 000 XXX
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// OPs: 000 - AND
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// 001 - OR
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// 010 - NAND
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// 011 - NOR
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// 100 - ADD
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// 101 - SUB
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module ALU(
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input var logic[2:0] opcode,
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input var logic[7:0] operandA,
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input var logic[7:0] operandB,
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output var logic[7:0] result
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);
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var logic[7:0] lu_result;
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LogicalUnit lu(
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.opcode(opcode),
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.operandA(operandA),
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.operandB(operandB),
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.result(lu_result)
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);
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var logic[7:0] au_result;
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ArithmeticUnit au(
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.opcode(opcode),
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.operandA(operandA),
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.operandB(operandB),
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.result(au_result)
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);
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// If the first most significant opcode bit is 0, it is a logical operation.
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always_comb case (opcode)
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3'b000,
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3'b001,
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3'b010,
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3'b011: result = lu_result;
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3'b100,
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3'b101: result = au_result;
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default: result = 0;
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endcase
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endmodule
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