44 lines
1.1 KiB
Systemverilog
44 lines
1.1 KiB
Systemverilog
`default_nettype none
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// Regs: 000 - reg0 (Constant load)
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// 001 - reg1 (ALU operandA)
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// 010 - reg2 (ALU operandB)
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// 011 - reg3 (ALU result/conditional operand)
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// 100 - reg4 (General purpose A)
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// 101 - reg5 (General purpose B)
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module RegisterFile(
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input var logic clock,
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input var logic reset,
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input var logic save,
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input var logic[2:0] saveselector,
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input var logic[7:0] savebus,
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input var logic[2:0] loadselector,
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output var logic[7:0] loadbus,
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output var logic[7:0] aluoperandA,
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output var logic[7:0] aluoperandB,
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output var logic[7:0] aluresult
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);
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// Our data is stored in here
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var logic[7:0] registers[5:0];
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// Reset everything to 0 or save value
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always @(posedge clock or posedge reset)
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if (reset)
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for (int ii = 0; ii < 6; ii = ii + 1)
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registers[ii] <= 8'b0;
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else
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if (save)
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registers[saveselector] <= savebus;
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// Load selected register value to loadbus
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assign loadbus = registers[loadselector];
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// Always propagate contents of ALU registers
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assign aluoperandA = registers[1];
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assign aluoperandB = registers[2];
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assign aluresult = registers[3];
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endmodule
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