21 lines
520 B
Systemverilog
21 lines
520 B
Systemverilog
`default_nettype none
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// Inst: MD OP
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// 01 000 XXX
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// OPs: 100 - ADD
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// 101 - SUB
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module ArithmeticUnit(
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input var logic[2:0] opcode,
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input var logic[7:0] operandA,
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input var logic[7:0] operandB,
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output var logic[7:0] result
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);
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// If the least significant opcode bit is 0, it is an addition
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always @(opcode or operandA or operandB) case (opcode)
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3'b100: result = operandA + operandB;
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3'b101: result = operandA - operandB;
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default: result = 0;
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endcase
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endmodule
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