108 lines
7.2 KiB
Plaintext
108 lines
7.2 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2020 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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# Date created = 11:27:08 März 23, 2023
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# CPU_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CGXFC5C6F27C7
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set_global_assignment -name TOP_LEVEL_ENTITY Counter_TestBench
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:27:08 MäRZ 23, 2023"
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set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
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set_global_assignment -name SYSTEMVERILOG_FILE RegisterFile.sv
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set_global_assignment -name SYSTEMVERILOG_FILE LogicalUnit.sv
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set_global_assignment -name SYSTEMVERILOG_FILE InputOutput.sv
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set_global_assignment -name SYSTEMVERILOG_FILE Counter.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ConditionalUnit.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ArithmeticUnit.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ALU.sv
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH Counter_TestBench -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_NAME ALU_TestBench -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ALU_TestBench
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ALU_TestBench -section_id ALU_TestBench
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set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
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set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 10000
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set_global_assignment -name BOARD "Cyclone V GX Starter Kit"
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set_global_assignment -name EDA_TEST_BENCH_NAME LogicalUnit_TestBench -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id LogicalUnit_TestBench
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME LogicalUnit_TestBench -section_id LogicalUnit_TestBench
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set_global_assignment -name SYSTEMVERILOG_FILE LogicalUnit_TestBench.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ArithmeticUnit_TestBench.sv
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set_global_assignment -name EDA_TEST_BENCH_NAME ArithmeticUnit_TestBench -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ArithmeticUnit_TestBench
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ArithmeticUnit_TestBench -section_id ArithmeticUnit_TestBench
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set_global_assignment -name SYSTEMVERILOG_FILE ALU_TestBench.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ConditionalUnit_TestBench.sv
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set_global_assignment -name EDA_TEST_BENCH_NAME ConditionalUnit_TestBench -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ConditionalUnit_TestBench
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ConditionalUnit_TestBench -section_id ConditionalUnit_TestBench
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set_global_assignment -name SYSTEMVERILOG_FILE RegisterFile_TestBench.sv
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set_global_assignment -name EDA_TEST_BENCH_NAME RegisterFile_TestBench -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id RegisterFile_TestBench
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME RegisterFile_TestBench -section_id RegisterFile_TestBench
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set_global_assignment -name SYSTEMVERILOG_FILE Counter_TestBench.sv
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set_global_assignment -name EDA_TEST_BENCH_FILE ALU_TestBench.sv -section_id ALU_TestBench
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set_global_assignment -name EDA_TEST_BENCH_FILE LogicalUnit_TestBench.sv -section_id LogicalUnit_TestBench
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set_global_assignment -name EDA_TEST_BENCH_FILE ArithmeticUnit_TestBench.sv -section_id ArithmeticUnit_TestBench
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set_global_assignment -name EDA_TEST_BENCH_FILE ConditionalUnit_TestBench.sv -section_id ConditionalUnit_TestBench
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set_global_assignment -name EDA_TEST_BENCH_FILE RegisterFile_TestBench.sv -section_id RegisterFile_TestBench
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set_global_assignment -name EDA_TEST_BENCH_NAME Counter_TestBench -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Counter_TestBench
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Counter_TestBench -section_id Counter_TestBench
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set_global_assignment -name EDA_TEST_BENCH_FILE Counter_TestBench.sv -section_id Counter_TestBench
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |