84 lines
1.8 KiB
Systemverilog
84 lines
1.8 KiB
Systemverilog
`default_nettype none
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module Decoder_TestBench;
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var logic clock, reset;
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tri fetch, decode, execute, writeback;
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Decoder dec(
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.clock(clock),
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.reset(reset),
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.fetch(fetch),
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.decode(decode),
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.execute(execute),
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.writeback(writeback)
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);
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// synthesis translate_off
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initial begin
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$timeformat(-9, 2, " ns", 20);
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$display("%0t Initial Reset", $time);
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clock = 1'b0;
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#20 reset = 1'b1;
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#20 reset = 1'b0;
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assert(fetch == 1'b0);
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assert(decode == 1'b0);
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assert(execute == 1'b0);
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assert(writeback == 1'b0);
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$display("%0t Fetch", $time);
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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assert(fetch == 1'b1);
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assert(decode == 1'b0);
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assert(execute == 1'b0);
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assert(writeback == 1'b0);
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$display("%0t Decode", $time);
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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assert(fetch == 1'b0);
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assert(decode == 1'b1);
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assert(execute == 1'b0);
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assert(writeback == 1'b0);
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$display("%0t Execute", $time);
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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assert(fetch == 1'b0);
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assert(decode == 1'b0);
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assert(execute == 1'b1);
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assert(writeback == 1'b0);
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$display("%0t Writeback", $time);
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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assert(fetch == 1'b0);
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assert(decode == 1'b0);
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assert(execute == 1'b0);
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assert(writeback == 1'b1);
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$display("%0t Fetch", $time);
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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assert(fetch == 1'b1);
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assert(decode == 1'b0);
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assert(execute == 1'b0);
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assert(writeback == 1'b0);
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$display("%0t Reset", $time);
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clock = 1'b0;
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#20 reset = 1'b1;
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#20 reset = 1'b0;
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assert(fetch == 1'b0);
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assert(decode == 1'b0);
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assert(execute == 1'b0);
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assert(writeback == 1'b0);
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$display("Success!");
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end
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// synthesis translate_on
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endmodule |