47 lines
1.2 KiB
Systemverilog
47 lines
1.2 KiB
Systemverilog
`default_nettype none
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module Decoder(
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input var logic clock,
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input var logic reset,
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output var logic fetch,
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output var logic decode,
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output var logic execute,
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output var logic writeback
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);
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var logic was_reset;
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var logic setvalue;
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var logic[1:0] reset_val;
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var logic[1:0] mode;
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Counter #(.WIDTH(2)) mode_cnt(
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.clock(clock),
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.reset(0),
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.decrement(0),
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.setvalue(setvalue),
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.valuein(reset_val),
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.valueout(mode)
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);
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always @(posedge clock or posedge reset) if (reset) begin
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// Set each output to 0 by setting was_reset.
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was_reset = 1'b1;
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// Also we already prepare the counter reset for the next clock, as the clock already
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// happened when this is "executed".
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setvalue = 1'b1;
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reset_val = 2'b00;
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end else if (was_reset == 1'b1) begin
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// The counter uses the same clock as this, so the reset is performed "now".
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// We can now "reset the reset" and continue counting regularly.
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was_reset = 1'b0;
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setvalue = 1'b0;
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reset_val = 2'b00;
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end
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assign fetch = ~was_reset && (mode == 2'b00);
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assign decode = ~was_reset && (mode == 2'b01);
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assign execute = ~was_reset && (mode == 2'b10);
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assign writeback = ~was_reset && (mode == 2'b11);
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endmodule |