65 lines
1.3 KiB
Systemverilog
65 lines
1.3 KiB
Systemverilog
`default_nettype none
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module Counter_TestBench;
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var logic clock;
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var logic reset;
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var logic decrement;
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var logic setvalue;
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var logic[7:0] valuein;
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tri[7:0] valueout;
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Counter cnt(
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.clock(clock),
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.reset(reset),
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.decrement(decrement),
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.setvalue(setvalue),
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.valuein(valuein),
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.valueout(valueout)
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);
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// synthesis translate_off
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integer ii;
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initial begin
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$timeformat(-9, 2, " ns", 20);
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$display("%0t Initial Reset", $time);
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#20 reset = 1'b1;
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#20 reset = 1'b0;
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assert (valueout == 1'b0);
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$display("%0t Increment 1024x", $time);
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decrement = 1'b0;
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for (ii = 0; ii < 1024; ii = ii + 1) begin
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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assert (valueout == 8'(ii + 1));
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end
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$display("%0t Decrement 1024x", $time);
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decrement = 1'b1;
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for (ii = 1024; ii > 0; ii = ii - 1) begin
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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assert (valueout == 8'(ii - 1));
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end
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$display("%0t Setvalue", $time);
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decrement = 1'b0;
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setvalue = 1'b1;
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valuein = 8'b00001111;
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#20 clock = 1'b1;
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#20 clock = 1'b0;
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assert (valueout == 8'b00001111);
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$display("%0t Reset", $time);
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#20 reset = 1'b1;
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#20 reset = 1'b0;
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assert (valueout == 8'b0);
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$display("Success!");
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end
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// synthesis translate_on
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endmodule |