diff --git a/CPU.qsf b/CPU.qsf
index c286bda..72584f6 100644
--- a/CPU.qsf
+++ b/CPU.qsf
@@ -108,7 +108,6 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name SYSTEMVERILOG_FILE CPU_TestBench.sv
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name EDA_TEST_BENCH_NAME CPU_TestBench -section_id eda_simulation
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id CPU_TestBench
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME CPU_TestBench -section_id CPU_TestBench
@@ -119,4 +118,5 @@ set_global_assignment -name EDA_TEST_BENCH_FILE ArithmeticUnit_TestBench.sv -sec
 set_global_assignment -name EDA_TEST_BENCH_FILE ConditionalUnit_TestBench.sv -section_id ConditionalUnit_TestBench
 set_global_assignment -name EDA_TEST_BENCH_FILE RegisterFile_TestBench.sv -section_id RegisterFile_TestBench
 set_global_assignment -name EDA_TEST_BENCH_FILE Counter_TestBench.sv -section_id Counter_TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE Decoder.sv -section_id Decoder_TestBench
\ No newline at end of file
+set_global_assignment -name EDA_TEST_BENCH_FILE Decoder.sv -section_id Decoder_TestBench
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Controller.sv b/Controller.sv
index 4f37393..f9d0bc5 100644
--- a/Controller.sv
+++ b/Controller.sv
@@ -5,11 +5,13 @@ module Controller(
   input var logic reset,
   input var logic[7:0] databus,
 
+  // Fixed outputs
   output var logic[1:0] opcode,
   output var logic[5:0] arg,
   output var logic[2:0] arg0,
   output var logic[2:0] arg1,
   
+  // Outputs depending on opcode
   output var logic regs_set,
   output var logic[2:0] regs_savesel,
   output var logic[2:0] regs_loadsel,